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CNFET is one of the most promising candidates for a building block of post silicon era integrated circuits due to its excellent electronic properties. The presence of unwanted metallic tubes is identified as a major challenge towards building robust CNT based circuits. Metallic tubes negatively impact the performance, power and yield of CNFET-based circuits. Current CNT growth techniques described in the literature show a wide range, from close to 4% to almost 40%, of metallic tubes being initially present in CNFETs. We used Monte Carlo simulation to analyze yield improvement techniques in both cases; (1) when metallic tubes are present in CNFETs, and (2) when they are removed with extra processing techniques proposed by researches. We proposed design-based promising methods for yield improvement. Suggested and analyzed yield-improvement techniques include transistor, gate and circuit level approaches.

The presence of metallic tubes and CNT diameter variation impacts delay of critical paths in CNFET circuits. Consequently, variations in critical path delays impact functional yield. We propose to predict circuit performance and yield using a statistical approach, rather than the worst-case method, to the critical path delay evaluation. We consider the CNT diameter variation and the number of tubes per transistor variation caused by the removal of unwanted metallic tubes. For the set of ISCAS'85 combinational benchmark circuits, we tested with initial presence of 10% and 20% metallic tubes, that are all being removed, we are able to show a functional yield between 92.04% and 99.95%, and between 20.95% and 94.05%, respectively. We assumed delay degradation not larger than 1.3x as compared to the initial 0% of metallic tubes. The algorithm proposed to statistically evaluate path delay in the presence of variations has a time complexity of O(V log V +VE), where E is the number of gates and V is the number of nodes in the circuit. The results show the reduction of statistically calculated critical path delay as compared to the worst-case calculations. This indicates that it would be possible to manufacture a CNFET-based circuit with acceptable delay and functional yield, even in the presence of fabrication imperfections. To predict the behavior of these circuits and to design them efficiently it is necessary to use a statistical approach to the design process.

Carbon nanotube field-effect transistor (CNFET) is one of the most promising candidates for a building block of post silicon era integrated circuits. One of the major challenges faced by the CNFET is the presence of unwanted metallic tubes that adversely impacts the delay, power, and functional yield of carbon nanotube (CNT) based circuits. In this paper, we present tradeoff between these parameters with the help of Monte Carlo simulations for basic logic gates designed using four different configurations of CNFET including two stacking configurations that we originally proposed in 2008. We present newly developed analytical models to estimate the functional yield of logic gates designed using four different configurations of CNFET. The absolute difference in functional yield magnitudes between the Monte Carlo simulations and analytical models for different percentage of metallic tubes and different drive strength of logic gates is 0% to 0.9% for inverter and 0% to 2.5% for NAND/NOR gates. Results indicate that the proposed stacking configurations have the potential to increase the functional yield by as much as 2X for inverter and 10X for NAND gate. This increase in functional yield was observed for 10X lower static power and for 4.1X-4AX delay penalty under iso-input capacitance.

One of the major challenges faced by CNFET technology is unwanted growth of metallic tubes that adversely affect the performance, power, and yield of circuits designed with CNFETs. Selective Chemical Etching (SCE) and VLSI-Compatible Metallic-Carbon-Nanotube Removal (VMR) techniques have been proposed to remove the unwanted metallic tubes. Unfortunately, both of these techniques also remove a large fraction of semiconducting tubes. Tube removal can result in degradation of circuit performance and non-functioning open-circuit logic gates. We have developed analytical models to quickly estimate the functional yield of CNFET-based circuits, in the presence of metallic tubes, and after their removal. The absolute difference in functional yield magnitudes between Monte Carlo simulations and our analytical models differ between 0.4% and 2.6% for an inverter, and between 0.2% and 3.4% for NAND/NOR gates.

This paper presents a comprehensive analysis of the impact of CNT fabrication imperfections on the performance of multichannel Carbon Nanotube FET (CNFET) -based devices. In particular, we introduce a methodology for stochastically estimating the impact of spacing between adjacent tubes and the impact of its variation. This enables accurate prediction of the reduction in drive current due to the removal of tubes, the increase in spacing between adjacent tubes, and variations in tube diameter and spacing. In multichannel CNFETs, when the number of channels (CNTs) is greater than eight, our experiments show that variations in tube diameter and inter-tube spacing result in less than 8% performance variation. Monte Carlo simulation results, however, show that the removal of tubes increases variation in I ON from 13% to 26% due to larger variation in inter-tube spacing. The presented realistic analysis and the proposed methodology can be extremely useful in variation-tolerant CNFET-based circuit design.

This paper analyzes the functional yield of CNFET based circuits when the metallic tubes are removed by extra processing steps. Functional yield for various gates is obtained through both Monte-Carlo (MC) simulations and analytical models. Tube Level Redundancy (TLR) is proposed to increase the functional yield of gates to an acceptable level when a large fraction of tubes are removed. Our results are very promising and indicate that when critical paths are considered, almost 100% yield can be achieved for relatively complex systems.

Carbon Nanotube FET (CNT-FET) is a promising candidate for the construction of future integrated circuits. However the presence of metallic tubes negatively affects delay, leakage power, and yield of such circuits. In this paper we compare four different CNT-FET configurations - shared tube, parallel tubes, transistor stacking, and tube stacking. In the presence of 10% metallic tubes, stacking configurations have potential to as much as double the yield for 4.1-4.4X delay penalty under iso-input capacitance and 3-7X lower leakage power compared to the non-stacked configurations. Analytical model and Monte Carlo simulation results for various logic gate sizes clearly indicate that an architecture that utilizes an appropriate combination of all four configurations is required to enable a better trade-off between delay, leakage power, and yield in the presence of metallic tubes.