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This article presents a compact quantum threshold voltage (${V}_{\text {th}}$) shift model for a junctionless (JL) quadruple-gate (QG) FET in subthreshold region. Starting from our previous compact model for JL QG FET, the potential and the classical electron density are calculated. Considering 2-D quantum confinement, four types of quantum systems are modeled as a combination of quantum harmonic oscillator (QHO) and quantum well with bottom perturbation potential, depending on the device dimensions. Electron subband energy level for each quantum system is analytically derived to get quantum electron density. The quantum ${V}_{\text {th}}$ shift model is obtained by the ratio of quantum and classical electron line density. The modeling results are validated by 3-D numerical device simulation. It is shown that the proposed model can accurately capture the quantum ${V}_{\text {th}}$ shift in JL QG FET where both fin width and height are 3 nm. Therefore, the proposed ${V}_{\text {th}}$ shift model can be used for quantum corrections for circuit simulation of JL QG FETs. [ABSTRACT FROM AUTHOR]

In the second part of this series, we propose a physics-based model for describing the temperature dependence of TiOx-based memristors, both switching and static. We show that the current–voltage (${I}$ – ${V}$) characteristics of memristor in the nonswitching regime, indicating a Schottky emission mechanism, can be described by minor modifications to the Schottky current equation. This leads to a physics-based static ${I}$ – ${V}$ compact model. Simultaneously, we show that the temperature dependence of the switching dynamics model parameters naturally emerges as a mere scaling factor from the static ${I}$ – ${V}$ model. This is a computationally efficient approach, which does not require any additional parameters to extend the switching dynamics model for incorporating thermal dependence. [ABSTRACT FROM AUTHOR]

We present a compact model of polycrystalline ferroelectric (FE) capacitors. The polycrystalline thin-film material is modeled as a collection of independent grains or grain groups. Each grain or grain group is characterized by its local field-dependent switching rate, which is characterized by a distribution function such as Gaussian or type-2 generalized beta distribution. This computationally efficient model accurately reproduces the published experimental polarization switching waveforms and the switching current waveforms in response to all reported applied voltage waveforms. The model tracks the polarization history so that it can simulate the transition between major and minor and among minor loops as well as accumulative polarization which cannot be captured by the conventional models. This model is intended for simulating circuits containing FE capacitors using commercial SPICE simulators for arbitrary applied voltage waveforms. It also has the capability of simulating the discrete switching and device variability in small-area FE capacitors having a small number of grains, although there is no available experimental data to check the model accuracy in this regard. [ABSTRACT FROM AUTHOR]

The lumped-charge (LC) technique is widely used to develop simple and physically based power device models for circuit simulators. The existing models, due to the linearization of the diffusion equations in the drift region, have some limitations that impact accuracy and numerical stability. In this work, the carriers’ transport equations, rather than linearized, are treated as differential equations, and an LC model that exactly solves the diffusion equations is presented. It improves the accuracy of the traditional models and provides a numerically stable expression of the currents while keeping the same simplicity. Furthermore, the continuity equations are rigorously discretized by means of the box integration method, widely used in finite element device simulators, which has been proven to be numerically stable and accurate. The new model is verified both on the static and transient characteristics of commercial insulated-gate bipolar transistors and power diodes. [ABSTRACT FROM AUTHOR]

A dynamic current model for the double gate negative capacitance field-effect transistor (NCFET) of the metal–ferroelectric–insulator–semiconductor (MFIS) structure is presented in this work. With a damping parameter ρ in the Landau–Khalatnikov (LK) theory for general ferroelectric (FE) materials, the gate control equation of NCFET is intrinsically dynamic which is solved directly as a basis of NCFET modeling. With the time-dependent charge densities at the source and drain sides, a dynamic current model is formulated analytically for the first time, considering the dynamic terms in a self-consistent way. The model has been verified with numerical TCAD simulations. It accurately reproduces the static negative capacitance (NC) effect in enhancing the driving current, as well as the dynamic NC effect, in the conduction delay and hysteresis for a wide range of NCFET parameters. The dynamic model after implementations is successfully applied to circuit simulations such as ring oscillators without convergence issues. [ABSTRACT FROM AUTHOR]

This article presents a compact model for the drain current and capacitances of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). The model is valid in the deep and tail states regions of operations, with a smooth transition between the two. The model parameters were extracted independently in the two regions using the unified model and extraction method (UMEM). The subthreshold regime and series resistances are considered for the drain current modeling. For the capacitances, it was found that the bias-dependent parasitic capacitances play a dominant role. The model was validated with TCAD simulations, with very good agreement. [ABSTRACT FROM AUTHOR]

A comprehensive investigation on the hot-carrier-induced interface state generation and its impact on carrier mobility in nMOSFET is performed. I – V compact modeling and charge pumping (CP) characterization are used as independent ways to evaluate the interface state density as a function of hot-carrier-induced aging. From the two techniques, similar power-law time exponents of the interface state density kinetics are obtained. Assisted by the quasi-spectroscopic (temperature-resolved) CP measurement, the extracted interface state density is further correlated with the I – V modeling results: an universal mobility degradation normalization parameter Nit,ref = ~ 4.1 × 1011/cm2 is reported, irrespective of the effective oxide thickness (EOT), stress temperature, or the relative degradation of the device under test (DUT). Supported by the fundamental principles deployed in the derivation and the broad range of experimental conditions considered for its validation, the reported normalization parameter could serve as a modeling constant in the commonly used I – V compact models to correlate the mobility degradation with the interface state density induced by hot carrier stress. [ABSTRACT FROM AUTHOR]

A thin film transistor (TFT) model applicable to circuit design is presented. The model is based on a general solution of the vertical 1-D Poisson equation, valid for asymmetric and independent top and bottom gates and for doped semiconductor films, with no restrictive approximations. The solution is necessarily numerical, but we describe a discretization strategy on a reduced and highly nonuniform grid, resulting in a computationally efficient model. The resulting long-channel model is complemented with empirical short-channel effect corrections. The model results are validated against measured c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) MOSFET data. [ABSTRACT FROM AUTHOR]

In this article, we report the development of a novel physics-based analytical model for explaining the current–voltage relationship in Schottky barrier (SB) 2-D-material field effect transistors (FETs). The model has at its core the calculation of the surface-potential (SP) which is accomplished by invoking 2-D density of states in conjunction with Fermi–Dirac (FD) distribution for electron and hole statistics. The explicit computation for the SP, carried out using the Lambert-W function together with Halley’s method, is used to construct the SP-based band-diagram for realizing the transparency of the SBs. Thereafter, the ambipolar current is derived in terms of the electron and hole injection phenomena—the thermionic emission and Fowler–Nordheim tunneling mechanisms—at the SB contacts. Furthermore, drift-diffusion current is derived in terms of the SP and incorporated in the model to account for the scattering in the intrinsic 2-D channel. Finally, the Verilog-A model is validated against experimental I-V data reported in the literature for two different 2-D-material systems. This is the first demonstration of an explicit SP-based SPICE model for ambipolar SB-2-D-FETs that is simultaneously built on tunneling-emission and drift-diffusion formalisms. [ABSTRACT FROM AUTHOR]

In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of g (the coefficient of polarization gradient effect) results in improved subthreshold slope, smaller OFF-current, smaller drain-induced barrier lowering (DIBL), and smaller output conductance. Inclusion of the polarization gradient effect in the NCFET compact model improves usability because it accurately captures the effects of negative DIBL and negative output conductance. [ABSTRACT FROM AUTHOR]

We present a Verilog-A based compact model for the superconductor-insulator-superconductor (SIS) Josephson junction. The model can generate both hysteretic and non-hysteretic current-voltage (I-V) response for the SIS junctions utilizing the Stewart-McCumber parameter. We calibrate our model with different SIS samples and demonstrate accurate matching between the simulated and experimental results. We implement temperature effect on the energy gap and the critical current of the superconductor to explore the dynamic trends in device characteristics. We calculate the junction inductance and energy as functions of junction current and temperature. We simulate the read/write operations of an SIS junction based cryogenic memory cell to illustrate the usability of our model. [ABSTRACT FROM AUTHOR]

The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator–semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NC-FDSOI model is computationally efficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators. [ABSTRACT FROM AUTHOR]

In this article, we report a physics-based compact model of drain current for InAs-on-insulator MOSFETs. The quantum confinement effect has been incorporated in the proposed model by solving the 1-D Schrödinger–Poisson equations without using any empirical model parameter. The model accurately captures the variation of surface potential, charge density in the inversion layer, and subband energy levels with gate bias inside the quantum well. The conduction-band nonparabolicity effect on modification in eigenenergy, effective mass, and density of states is derived and incorporated into the proposed model. The velocity overshoot effect that originates from the quasi-ballistic nature of carrier transport is also considered in the model. The proposed drain current model has been implemented in Verilog-A to use in the SPICE environment. The model predicted results are in good agreement with the commercial device simulator results and experimental data. [ABSTRACT FROM AUTHOR]

Recent progress has demonstrated that current-induced domain wall motion (CIDWM) is able to achieve efficient and ultrafast magnetic switching in the case of spin–orbit torque (SOT) and Dzyaloshinskii–Moriya interaction (DMI). CIDWM-based devices are taken as promising candidates for the next-generation nonvolatile artificial neurons and synapses due to its excellent programmability, fast operation speed, low write power, and so on. In this article, we present a physics-based model of CIDWM magnetic tunnel junction (MTJ), which exhibits high performance based on experimental results. The proposed model integrates the CIDWM dynamics and nanowire MTJ resistance, showing great agreement with extensive physical simulation. A learning circuit based on CIDWM-MTJ, as a hybrid MTJ/CMOS circuit example, has been designed and simulated to validate its functionality. The proposed SPICE-compatible compact model will be useful for high-performance circuit and system evaluation and is expected to promote the research and development of CIDWM-based spintronics devices. [ABSTRACT FROM AUTHOR]

The lifetime of organic thin-film transistors (OTFTs) is known to be significantly shorter than that of silicon MOSFETs. It is therefore important to be able to predict their degradation early in the design phase. In this paper, OTFT current characteristic variation is studied in measurements of fabricated devices. In addition, we propose a drain-current simulation model that incorporates temporal parameter variation. The proposed model expresses parameter degradations as changes in threshold voltage and carrier mobility. With the extracted parameters, our proposed model successfully reproduces the temporal performance degradation observed in fabricated devices. We compared our proposed model with existing parameter variation models by fitting with measurement results. Root mean square errors (RMSEs) were calculated for each model. Our proposed model achieved an RMSE of 2.26% whereas that of the existing model was 9.80%. Oscillation frequency degradation in an organic ring oscillator (RO) circuit was also simulated to compare with the measurement results. The simulation results adequately captured the degradation trend observed in the measured results. [ABSTRACT FROM AUTHOR]

In this brief, we present a quasi-static compact model for bipolar ReRAM memristive devices. This model is based on a piecewise model in flux-charge space for reset and set transitions that has been extended to build a compact model of reset/set transitions for different slopes. In order to show its functionality, we use it to reproduce the behavior of a device fabricated by the CNR-IMM, MDM Laboratory. We discuss the needed parameters extraction procedure for the device. As shown in the results, the implemented model is able to capture the effects of the slope change in the ramp input signal for reset and set by using a set of technological parameters related to the device and information related to the slope of the ramp input voltage signal. [ABSTRACT FROM AUTHOR]

A multiscale technology computer-aided design (TCAD) simulation methodology is presented to calculate the intrinsic transit time of InP double heterojunction bipolar transistors (DHBTs). A 2-D hyd-rodynamic (HD) simulator is employed to produce the dc characteristics and electrostatic potentials of the selected devices. Utilizing the cuts of the obtained potential profiles as inputs, a 1-D full-band, atomistic quantum transport (QT) solver is then deployed to determine the ballistic electronic transport properties of these components. The transit times of DHBTs based on InGaAs/InP and GaAsSb/InP technologies are finally investigated with the proposed approach. Good qualitative agreements are observed with the experimental measurements. The observed underestimations of the experimental transit times are justified with the physics-based compact model HiCuM, thus providing a basis for structure and performance optimizations toward real terahertz transistors. [ABSTRACT FROM AUTHOR]

In this article, we illustrate the impact of the high electric field region and the effects of this has on the capacitance–voltage characteristics of a GaN HEMT device. Such effects arise due to a significant spike in the electric field near the drain-side edge of the gate electrode. The presence of the high electric field has a direct impact on the intrinsic capacitances of the device. We present a physics-based compact model for the gate charge and intrinsic capacitances, which captures these effects. TCAD simulations are performed to analyze the underlying principles of such phenomena while providing validation for the proposed model. The advanced SPICE model for GaN HEMTs (ASM-GaN-HEMT) is adopted and modified to include the effects of the high electric field region. The simulation results are in excellent agreement to the TCAD and the measured data. The model is compared to simulations that neglect such effects in order to illustrate the importance of capturing the impact of high-field region on the intrinsic device capacitances. [ABSTRACT FROM AUTHOR]

Silicon-thickness scaling has been used as the main parameter for short-channel-effect (SCE) reduction. Nevertheless, SCEs are still present in advanced thin-layer MOSFETs. Here, for enlarging the insight into SCE suppression, a new compact model is developed based on the SCE origin, which is demonstrated to be the potential distribution at the contact/channel junctions. In addition, it is shown that the potential distribution along the MOSFET channel can be modeled by overlapping potentials coming from the source and drain sides. The developed compact model is verified with leading-edge multi-gate MOSFETs, further demonstrating that device optimization with SCE suppression becomes possible due to the accurate reproduction of the device characteristics. The model validation is done with 2-D device simulations for different channel lengths, oxide, and silicon thicknesses as well as channel-doping concentration, for which an accurate compact-model reproduction is achieved. In addition, the general properties of the potential-based SCE model are extended to other MOSFET device structures. [ABSTRACT FROM AUTHOR]

This paper presents a unified physics-based insulated-gate bipolar transistor (IGBT) compact model for circuit simulation that predicts the performance of both Si and SiC, n- and p-channel devices. The model can predict the detailed switching waveforms of these technologies based on its charge-based formulation. Further, this compact IGBT model is presented alongside a unique datasheet-driven parameter extraction process. The parameter extraction process enables users to quickly extract model parameters from data typically published without the need of taking physical measurements. The model has been validated with both Si and SiC devices for static and dynamic characteristics. The SiC IGBTs used for validation are a 12.5-kV n-channel device and a 13-kV p-channel device, while the Si IGBT chosen was IXDH30N120 from IXYS Corp. (Milpitas, CA, USA). This is the only IGBT model that predicts the performance of both n- and p-channel, Si and SiC devices, providing more freedom for the development of complex power electronics circuit designs. The convergence of the model has been verified by implementing a complex circuit consisting of both a dc–dc converter and a dc–ac inverter. The results presented here show that the unified model can be used to describe the behavior of a wide range of Si and SiC IGBT circuits. This paper is accompanied by a Verilog-A source code and a power point file demonstrating the model parameter extraction sequence. [ABSTRACT FROM AUTHOR]

The second generation of the compact HiSIM_IGBT model for circuit simulation is reported. HiSIM_IGBT2 is developed on the basis of an adapted version of the high-voltage mosfet model HiSIM_HV and solves the Poisson equation along the complete device iteratively in a consistent way. The major HiSIM_IGBT2 improvement concerns the description of the mosfet contribution to the dynamically varying resistance effect in the base-region of the bipolar transistor (BJT) part of the insulated gate bipolar transistor (IGBT). An important finding is that the IGBT mostly operates under the high-injection condition, namely, under the drift mechanism for the transport of the injected carriers, and that a subtle balancing of the contributions from bipolar control and mosfet control of the IGBT is required. The developed model is verified with 2-D-numerical device simulation to accurately reproduce the potential distribution within the IGBT. Therefore, the specific IGBT features, induced by the highly resistive base region under the high-injection condition, are self-consistently captured. The developed model is proven to provide stable circuit simulations with accurate reproduction of the switching performances. [ABSTRACT FROM AUTHOR]

In this brief, we present an improved model of bulk charge effect for both drain current (${I}_{\text {DS}}$) and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model. The proposed model captures all the well-known and important bulk charge effects, as the Abulk term does for BSIM3/BSIM4. The model is validated with the experimental and technology computer-aided design (TCAD) data. The proposed model enhances the fitting accuracy for ${I}_{\text {DS}}$ , and more importantly its derivatives and capacitances too. [ABSTRACT FROM AUTHOR]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]

Physics-based compact models for redox-based resistive switching memory (ReRAM) devices are used to increase the physical understanding of the complex switching process as well as to allow for accurate circuit simulations. This includes that models have to cover devices showing bipolar switching (BS) and complementary switching (CS). In contrast to BS devices, which store the information in (at least) one high and one low resistance state, CS devices use (at least) two high resistance states. Applications of CS devices range from passive crossbar arrays to novel logic-in-memory concepts. The coexistence of CS and BS modes in one device has been shown experimentally. Here, a physics-based compact model describing BS and CS consistently is presented. Besides modeling CS devices, the model improves the description of BS as it allows to reproduce and explain anomalies in the BS RESET process. The model includes ion drift and diffusion along the filament. The influence of different parameters on the drift–diffusion balance is discussed. [ABSTRACT FROM AUTHOR]

A compact model for tunnel diode body contact (TDBC) silicon-on-insulator (SOI) n-MOSFETs was developed in this paper. The compact model is implemented in Verilog-A to simulate the dc and radio frequency (RF) performance of a TDBC SOI MOSFET. The TDBC SOI MOSFETs are successfully fabricated and are used to measure important transistor electrical parameters. The investigation results reveal that TDBC structure suppresses floating body effects (FBEs) as well as T-gate body (TB) contact structure and shows significant improvement in RF performance without introducing additional parasitic capacitances compared with the TB device. Kink phenomena and an abnormal subthreshold swing originating from FBEs are sufficiently suppressed. It is demonstrated that the TDBC SOI MOSFETs provide a promising concept for digital, analog, and RF applications. The outputs from this analytic model are in fair agreement with the TDBC experimental data, which validates the effectiveness and robustness of the compact model for TDBC SOI technology. Finally, good accuracy ensures that the proposed model is applicable for the implementation in circuit simulation tools. [ABSTRACT FROM AUTHOR]

The compact model of HIroshima-University Starc Igfet Model (HiSIM)_GaN for GaN-HEMT devices is reported, which solves the Poisson equation iteratively, in a similar way as the industry-standard compact HiSIM models for other semiconductor devices. The model considers all possible charges induced within the device, including the dynamically varying trap density. It is verified that the model can reproduce the 2-D-device simulation results accurately. In particular, the operation frequency dependence of the current collapse can also be captured correctly based on the trap time constant. [ABSTRACT FROM AUTHOR]

The additional implanted channel-dopant layer of depletion-mode (DM) MOSFETs induces, at the same time, two main currents, namely, an accumulation current at the channel surface and a neutral-region current flowing deep in the implanted buried layer. In particular, the neutral-region current causes the normally-on condition of DM MOSFETs. These two currents dominate drain–source current alternatively depending on the bias conditions. To model the measured features of a DM MOSFET, a compact model is developed by considering also the complete vertical potential distribution from the surface to the bottom of the additional implanted channel-dopant layer. The potential distribution is self-consistently obtained by solving the Poisson equation. It is further demonstrated that a major development task is the correct coupling between Vds and Vbs contributions, which is needed to describe the specific features of the DM MOSFET accurately. [ABSTRACT FROM AUTHOR]

We report the first compact model to estimate the ${V}_{T}$ distribution of double gate-FinFET due to line edge roughness. We derive closed-form expressions, representing the compact model, for: 1) mean and standard deviation of fin width (${W}_{\text {fin}}$) in terms of geometrical and variability parameters of the FinFET; 2) ${V}_{T}$ as a function of ${W}_{\mathrm {fin}}$ for uniform width fins; and 3) ${V}_{T}$ in tapered fins using percolation. The ${V}_{T}$ distribution produced from the compact model shows a good match with well-calibrated TCAD data and demonstrates an excellent accuracy (~3mV rms error) for a wide range of scaling and variability parameters. The model is simple, platform independent, and $\sim {\text {10}}^{\text {4}}{\times }$ faster compared to TCAD. It enables intuitive understanding of design space for FinFET on the one hand, and accurate FinFET variability-aware circuits and system design on the other hand. [ABSTRACT FROM AUTHOR]

To accurately describe the electrical behaviors of organic field-effect transistors (OFETs) across the whole subthreshold regime, a compact model considering both non-exponential gate-voltage-dependent diffusion current and additional drift current is developed. The two current components in the subthreshold regime are combined into one closed-form expression with a hyperbolic tangent transition function. By fitting transfer and output curves in the subthreshold regime at different bias voltages, the model is shown to be applicable to OFETs in different materials and device structures of large and small subthreshold swings. The model is further demonstrated continuity with the OFF-state and above-threshold regimes when being incorporated into a commercial SPICE simulator for circuit simulations. [ABSTRACT FROM AUTHOR]

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET. [ABSTRACT FROM AUTHOR]

This paper presents a new physical compact model for interface state creation due to hot-carrier degradation in advanced SiGe heterojunction bipolar transistors (HBTs). An analytical model for trap density is developed through an accurate solution of the rate equation describing generation and annihilation of interface traps. The analytical aging law has been derived and implemented in terms of base recombination current parameters in HiCuM compact model and its accuracy has been validated against results from long-term aging tests performed close to the safe-operating areas of various HBT technologies. The model implementation uses a single additional node, alike previous implementations, thereby preserving its simplicity, yet improving the accuracy and the physical basis of degradation. [ABSTRACT FROM AUTHOR]

Junctionless transistors (JLTs) are presumed more scalable compared to other technologies, but its circuit performance is not fully understood. In this paper, we develop a charge-based compact model for a double-gate JLT (DGJLT) to explore the dc and the quasi-static performance of the transistor technology. First, 1-D Poisson's equation is solved analytically by using the Lambert function to obtain the (sheet) charge density in the channel. Second, a continuous charge-based drain current model is derived for long-channel DGJLTs using the Pao-Sah's dual integral. The model applies to all working regions (i.e., fully depleted, partly depleted, and accumulation). Third, based on the drain current, we develop the terminal charge model for ac and transient circuit simulation. Finally, the short-channel effect is modeled by adding an effective gate voltage to the proposed long-channel model. The compact model is validated by a numerical simulator over a wide range of voltage bias and device geometries. Results predicted by the analytical model agree well with numerical results. The model has been implemented in the Hspice circuit simulator with Verilog-A language and used to simulate a DGJLT inverter and oscillator without any convergence problem. [ABSTRACT FROM AUTHOR]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

We present a compact model for source-to-drain tunneling current in sub-10-nm gate-all-around FinFET, where tunneling current becomes nonnegligible. Wentzel–Kramers–Brillouin method with a quadratic potential energy profile is used to analytically capture the dependence on biases in the tunneling probability expression and simplify the equation. The calculated tunneling probability increases with smaller effective mass and with increasing bias. We at first use the Gaussian quadrature method to integrate Landauer’s equation for tunneling current computation without further approximations. To boost simulation speed, some approximations are made. The simplified equation shows a good accuracy and has more flexibility for compact model purpose. The model is implemented into industry standard Berkeley Short-channel IGFET Model-common multi-gate model for future technology node, and is validated by the full-band atomistic quantum transport simulation data. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices’ pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level. [ABSTRACT FROM PUBLISHER]

In this paper, we introduce a new compact model of the parasitic resistance of a FinFET with a hexagonal-shaped raised source–drain (S/D) structure. In contrast to previous models that divided the extrinsic S/D region into three parts, we redefined the region boundaries and modeled them as a series connection of accumulation resistance, gradient resistance, bulk resistance, and contact resistance. The newly added bulk resistance model accounts for the highly doped silicon region. We also significantly improved the contact resistance model to reflect the contact area and contact resistivity for better accuracy in the raised S/D region. We validated the accuracy of our model by varying the gate voltage, doping diffusion length, epitaxy silicon height, and contact resistivity, finding the model errors to be within 2% of the 3-D technology CAD device simulation results. [ABSTRACT FROM PUBLISHER]

A physics-based compact model for double-gate polysilicon thin-film transistors (TFTs) with a doped channel is proposed in this paper. Through the effective charge density approach, the electrostatic potential is solved explicitly from the Poisson’s equation without using the conventional regional approach. The resulting single-piece electrostatic potential equation, which does not consist of the intermediate parameter, offers clear physics meaning and good accuracy, particular when the TFT operates in the transition region. The TFT’s drain current model is then developed by integrating the electrostatic potential equation analytically with the Pao-Sah equation. Finally, the model is verified by numerical and experimental data. Such a compact model is highly suitable for circuit simulations. [ABSTRACT FROM PUBLISHER]

Thin-film transistors (TFT) in hydrogenated amorphoussilicon, amorphousmetal oxide, andsmallmolecule and polymer organic semiconductors would all hold promise as potential device candidates to large area flexible electronics applications. A universal compact dc model was developed with a proper balance between the physical and mathematical approaches for these thin-film transistors (TFTs). It can capture the common key parameters used for device performance benchmarking of the different TFTs while being applicable to a wide range of TFT technologies in different materials and device structures. Based on this model, a user-friendly tool was developed to provide an interactive way for convenient parameter extraction. The model is continuous from the off-state and subthreshold regimes to the above-threshold regime, avoiding the convergence problems when being used in SPICE circuit simulations. Finally, for verification, it was implemented into a SPICE circuit simulator using Verilog-A to simulate a TFT circuit examplewith the simulated results agreeing verywell with the experimental measurements. [ABSTRACT FROM AUTHOR]

In this letter, a semi-analytical current–voltage model for a negative capacitance field-effect transistor (NCFET) with a ferroelectric material (i.e., BaTiO3) is proposed. Surface potential ( \psi \mathrm {S}) in the channel region is determined first by solving the Landau–Khalatnikov (LK) equation numerically with Poisson’s equation. Then, the drain–current is achieved based on the current continuity equation using \psi \mathrm {S} determined earlier. In addition, by introducing a fitting potential for a given drain–voltage, threshold voltage shift can be captured, resulting in accurate surface potential and drain–current at different gate voltages. We have verified our model using the technology computer-aided design (TCAD)-MATLAB simulation, and our model exhibits an excellent agreement to the simulation results. In addition, the impacts of the ferroelectric thickness and channel doping concentration on the device performance and hysteresis window of NCFET are thoroughly explored. [ABSTRACT FROM AUTHOR]

We present a surface potential-based compact model for nanowire FETs, which considers 1-D electrostatics along with the effect of multiple energy subbands. The model is valid for any semiconductor material, cross-sectional geometry, and any channel length with transport regimes varying from drift-diffusive to quasi-ballistic. The model captures the phenomenon of quantum capacitance and the effect of temperature. We have validated it with numerical simulations and experimental data for Si, Ge, and InAs nanowires of different geometries. Circuit simulation has also been performed with the model. The physics-based model is accurate and can be used as a tool for analysis and prediction of the effects of geometry scaling, material dependence, and temperature variation on device and circuit characteristics. To the best of our knowledge, this is the first time a compact model for nanowire FETs is being presented, which includes multiple subbands along with geometry scaling while being valid for different degenerate and nondegenerate semiconductor materials. [ABSTRACT FROM AUTHOR]

We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal–ferroelectric–metal–insulator–semiconductor structure. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for surface potential and drain current in transition metal dichalcogenide (TMD) channel material-based n-type and p-type FETs. The model considers 2-D density of states and Fermi–Dirac statistics along with drift-diffusion transport model and includes velocity saturation and trap state effects. The developed model has been implemented in Verilog-A and is applicable for symmetric double gate as well as top-gated TMD-on-insulator FETs. The presented model is extensively validated with simulation as well as experimental data for different TMD materials-based FETs and shows excellent agreement with both the simulation and the experimental data. We further validate the model at circuit level using experimental data of MoS2 FET-based inverter. [ABSTRACT FROM AUTHOR]

A trap-density-based compact model of dynamic metal-oxide semiconductor field-effect transistor degradation due to hot electrons is reported, for which model parameters are extractable from measured 1/ f noise properties. It is observed that the deep trap-state increase is dominant for the degradation and approaches its maximum under long accelerated-stress duration. A key modeling concept is the explicit inclusion of the extracted stress-condition-dependent trap density in the Poisson equation, which is solved iteratively. The developed model correctly predicts actual dynamic degradation of the measured I-V characteristics, that is, trap density increase during stress application, without the disadvantage of longer simulation times. The reported model can automatically reproduce not only the threshold-voltage shift, but also the degradation of the complete I – V characteristics and all other observable effects caused by the carrier trapping, without any additional model-parameter fitting for each of these effects. [ABSTRACT FROM PUBLISHER]

A predictive tunnel FET compact model is proposed. Gaussian quadrature method is used to overcome the challenge of integration. This provides the flexibility to use Wentzel–Kramers–Brillouin under spatially varying electric field, to incorporate effective band edge states broadening, and to evaluate the drain current by Landauer equation with consideration of electron reflection at the tunnel junction. The model not only shows good accuracy, speed, and smoothness, but is also some predictive capability so that the effects of changing material parameters on IC characteristics are well captured. The model is validated with atomistic simulation data for several materials. [ABSTRACT FROM PUBLISHER]

A new model to capture the physics of short channel double-gate junctionless transistor (DGJT) has been developed. By solving the 2-D Poisson’s equation, the channel potential solution is obtained for both the physical channel and the dynamic channel extension to the source and drain. This dynamic change in channel boundary in DGJT has a strong impact on the performance of junctionless transistor, especially at reduced channel length. Based on the channel potential solution, a smooth and continuous drain current model is derived from Pao–Sah’s dual integral. This model is valid for all operation modes, including full depletion, partial depletion, and accumulation. Extensive comparison with numerical simulation has been performed to validate model in both the long channel and short channel regimes. [ABSTRACT FROM PUBLISHER]

Surface-potential-based drain current model is presented for organic thin-film transistors considering both exponential deep and tail trap states densities. The model is derived on the basis of the assumption that the trapped carrier concentration dominates Poisson’s equation. An analytical drain current expression is obtained. The expression is valid in both subthreshold and above-threshold regimes. The calculated results are verified by available experimental data at different temperatures. [ABSTRACT FROM AUTHOR]

Two-section models for capturing the lateral ac emitter-current crowding effect, which is also known as the lateral nonquasi-static (NQS) effect, are presented following a consistent approach based on a model formulation for ac operating condition. Following the theoretical results, model formulations suitable for implementation in the large-signal domain are developed. The proposed two-section model performs better than the state-of-the-art model in both the large-signal and small-signal domains and appears to be suitable for accurately capturing the lateral NQS effect. [ABSTRACT FROM AUTHOR]

A compact model for generic heterojunction tunnel FETs (H-TFET) is developed to simulate H-TFET formed by different source/body material systems. The model is based on the device electrostatic potentials obtained from the solution of Poisson’s equation. After deriving the potential profile, the tunneling distance from the source to the channel is calculated by matching the boundary conditions between the two materials. The drain current, terminal charges, and capacitance are derived based on the electrostatics dictated by the tunneling distance. To improve the accuracy for lightly doped source H-TFET in p-type devices, the effect of source depletion is also included. The model has been implemented in a circuit simulator without convergence program. It has also been extensively verified by TCAD simulations and published data to show its validity. [ABSTRACT FROM AUTHOR]

Accurate description of the electrical behavior of organic solar cells (OSCs) becomes necessary with the advance of OSC technology toward up-scaled modules. We propose here a compact model for OSCs, by identifying different regimes present in the device operation in dark and under light: OFF, exponential sub- V\mathrm{\scriptscriptstyle ON} , power-law above- V\mathrm{\scriptscriptstyle ON} , and photocurrent. We also present a complete parameter extraction method for the model. In addition, we discuss the effect of the resistivity of transparent electrode and the device size on the OSC performance, by illustrating expected modifications on the current–voltage curve and parameter values. [ABSTRACT FROM PUBLISHER]