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The originally proposed superjunction (SJ) power MOSFET structure with interdigitated p-n columns is highly recognized for its higher voltage-blocking capability and lower specific ON-state resistance. However, in practice, the performance of 54 devices is greatly handicapped due to difficulties in the formation of perfect charge-balanced p-n columns by the limitation of fabrication process technology, particularly, for devices with small p-n column widths at low voltage ratings, Recently developed structures of polysilicon-flanked and oxide-bypassed SJ MOSFETs are to overcome the conventional 5,1 device fabrication limitation. The follow-up development on extending the scope of these recently reported device structures to lateral 5,1 structures, which is suitable for SJ power integrated circuits, Is reported for the first time, In this paper, detailed descriptions of the progressive development and the technical advancement of several Si MOSFET structures are presented with both simulation and experimental results. [ABSTRACT FROM AUTHOR]

The superjunction MOSFET power devices, such as p-n column superjunction (named SJ or CoolMOS) devices and oxide-bypassed (OB) devices, are highly recognized for their higher blocking capability and lower on-state resistance. However, the performance of SJ devices is greatly handicapped due to difficulties in formation of perfect charge-balanced SJ p-n columns by the current process technology, especially for devices with small widths and voltage ratings below 180 V. OB devices can be an alternative in this voltage region, which utilize the well established oxide thickness control in fabrication instead of the difficult doping control as in SJ devices. However, OB drift region electric field distribution is not as optimal as that in SJ devices. Gradient oxide-bypassed (GOB) structure enhances the performance of OB devices so that it can achieve a performance comparable to that of an ideal p-n column SJ device in the medium voltage range, and at the same time, requires simple process technology. Complete descriptions on the GOB device and related design issues are presented in this paper. Fabrication issues are also discussed with possible sacrificial materials and etchants for making the vertical graded oxide sidewalls. Design cases for 80, 120, and 180 V GOB devices are also illustrated for better understanding in the device. [ABSTRACT FROM AUTHOR]

The performance of specific on-state resistance (Ron,sp) versus breakdown voltage (Vbr) of a superjunction power MOSFET device is constrained by the quality of its sidewall junctions formed by neighbouring p and n columns in the drift region. The p–n junction quality, which is inevitably affected by the inter-column dopant diffusion in practice, will limit the Ron,sp–Vbr device performance if no compensation measure is taken. A detailed study of the influence of sidewall junction quality on performance at various column widths under given thermal process conditions was carried out through process and device simulations. The study discovers the practical optimal performance of superjunction (SJ) DMOS and UMOS structures under the influence of dopant inter-column diffusion. Analysis of the phenomenon shows that the degradation of the breakdown voltage is caused by the p and n column charge imbalance. Practical SJ performance equations, which model the influence reasonably well, are derived in the paper. These equations can be used to predict the practical performance of an SJ device under given thermal conditions, which in turn guides us to the compensation measures required to achieve better performance. [ABSTRACT FROM AUTHOR]

A new partial silicon-on-insulator (SOI) formation technology and the associated RF LDMOSFET device structure on silicon bulk substrate are proposed in this paper. The same technology can also be applied to enhance the quality factor of the integrated on-chip microinductors. The proposed technology is able to reduce both drain/substrate parasitics and leakage current tier devices fabricated on bulk substrate. At the same time, the approach overcomes the thermal problem encountered by devices fabricated on full-SOI substrate. To demonstrate the technology, both partial-SOI LDMOSFET and microinductor devices were fabricated on bulk wafer with their RF performance verified by laboratory measurements. [ABSTRACT FROM AUTHOR]

Presents a study that proposed a novel folded gate LD metal oxide semiconductor transistor (FG-LDMOST) with the properties of low-on resistance and high transconductance. Information on how the FG structure was formed; Investigation of the FG concept; Fabrication of FG-LDNOS on 4-5 &Ω; cm n-type <100> lightly doped substrate using complementary metal oxide semiconductor (CMOS) compatible process technology.

Presents a study which proposed a novel silicon radio frequency metal oxide semiconductor field-effect transistor structure with a dummy-gate incorporated between the active gates. Analysis of the structure of the transistor; Experimental details; Conclusions.

The superjunction (SJ) MOSFET power device is highly recognized for its higher blocking capability and lower on-state resistance that breaks the conventional unipolar silicon limit. However, SJ devices below 100 V rating incur constraint of unrealistic narrower column widths [1], [2] and their performance is greatly handicapped due to difficulties in formation of perfect charge-balanced SJ p-n columns by current process technology. Based on the alternative approach of tunable oxide-bypassed (TOB) SJ MOSFET concept proposed in [15], a TOB-UMOS device of 79 V rating has been successfully fabricated for the first time. Laboratory measurements indicate that the device has broken the ideal SJ MOSFET performance line at equal column width of 3.5 µm, and potentially the ideal silicon limit as well. [ABSTRACT FROM AUTHOR]