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Abstract: Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, the recent mobility enhancement technologies including application of strain and new channel materials such as SiGe, Ge and III–V materials are reviewed. These carrier transport enhancement technologies can be classified into three categories; global enhancement techniques, local enhancement techniques and global/local-merged techniques. We present our recent results on MOSFETs using these three types of the technologies with an emphasis on the global strained-Si/SiGe/Ge substrates and the combination with the local techniques. Finally, issues on device structures merged with III–V materials are briefly described. [Copyright &y& Elsevier]

A novel fabrication method for ultra-thin Si1−xGex-on-insulator (SGOI) virtual substrates is proposed for the application of strained silicon-on-insulator (SOI) MOSFETs. Evaluation of the strain in a strained Si layer on this SGOI substrate is also presented. A 9-nm-thick SGOI layer with x=0.56 was formed by dry oxidation of epitaxially grown Si0.9Ge0.1 on a SOI substrate. During the oxidation, Ge atoms were rejected from the surface oxide layer and condensed in the remaining SGOI layer without introducing considerable threading dislocations. After removing the surface oxide layer, a 10-nm-thick Si layer was grown on the SGOI layer. TEM and Raman measurements indicated that the Si layer was pseudomorphically grown on the SGOI layer with 1.0% of tensile strain, corresponding to the strain in a Si layer on fully relaxed Si0.76Ge0.24. This fabrication method is applicable to fully depleted strained SOI MOSFETs with gate lengths of less than 100 nm, which require relaxed and thin SGOI layers (<10 nm) with high x value (x>0.3). [Copyright &y& Elsevier]

A promising fabrication method for a Si[sub 1-x]Ge[sub x]-on-insulator (SGOI) virtual substrate and evaluation of strain in the Si layer on this SGOI substrate are presented. A 9-nm-thick SGOI layer with x=0.56 was formed by dry oxidation after epitaxial growth of Si[sub 0.92]Ge[sub 0.08] on a silicon-on-insulator substrate. During the oxidation, Ge atoms were rejected from the surface oxide layer and condensed in the remaining SGOI layer, which was partially relaxed without introducing a significant amount of dislocations. It is found from the analysis of the Raman spectra that the strained Si layer grown on the SGOI layer involves a tensile strain of 1%. This strained Si on the SGOI structure is applicable to sub-100-nm metal–oxide–semiconductor field-effect transistors. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Abstract: We propose a novel method to form Ge nano-wire structures by utilizing a three-dimensional (3D) Ge condensation technique. Since this method needs only top-down and Si compatible processes, Ge nano-wire MOSFETs fabricated by this technique are suitable for actual LSI applications. Based on this concept, we have fabricated SiGe on insulator wire pMOSFETs with Ge content up to 92% and diameter down to 35 nm. 3× enhancement of transconductance against a control Si device has been demonstrated in pMOSFETs with Ge content of 79%, though the performance enhancement in the highest Ge content device has not been obtained yet because of the non-optimized 3D Ge condensation processes. Further performance enhancement is expected after optimizing 3D Ge condensation processes especially for higher Ge content SiGe channels. [Copyright &y& Elsevier]