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Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique
- Source :
-
Thin Solid Films . Nov2008, Vol. 517 Issue 1, p167-169. 3p. - Publication Year :
- 2008
-
Abstract
- Abstract: We propose a novel method to form Ge nano-wire structures by utilizing a three-dimensional (3D) Ge condensation technique. Since this method needs only top-down and Si compatible processes, Ge nano-wire MOSFETs fabricated by this technique are suitable for actual LSI applications. Based on this concept, we have fabricated SiGe on insulator wire pMOSFETs with Ge content up to 92% and diameter down to 35 nm. 3× enhancement of transconductance against a control Si device has been demonstrated in pMOSFETs with Ge content of 79%, though the performance enhancement in the highest Ge content device has not been obtained yet because of the non-optimized 3D Ge condensation processes. Further performance enhancement is expected after optimizing 3D Ge condensation processes especially for higher Ge content SiGe channels. [Copyright &y& Elsevier]
Details
- Language :
- English
- ISSN :
- 00406090
- Volume :
- 517
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- Thin Solid Films
- Publication Type :
- Academic Journal
- Accession number :
- 35070865
- Full Text :
- https://doi.org/10.1016/j.tsf.2008.08.054