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Total-ionizing-dose (TID) effects are compared in 1) conventional high-temperature processed planar fully-depleted silicon-on-insulator (FD-SOI) p-channel MOSFETs, 2) 3-D sequentially integrated (3DSI) FD-SOI MOSFETs in the bottom layer with additional thermal budget and process flows due to the creation of the top layer, and 3) 3DSI low-temperature-processed FD-SOI MOSFETs in the top layer. When irradiated under worst case negative bias, 3DSI bottom-isolated transistors show significantly enhanced charge trapping and transconductance degradation than planar devices. The enhanced degradation for bottom-isolated devices is attributed primarily to increased interface- and border-trap formation at the buried oxide (BOX)/Si interface and/or lateral charge nonuniformities in the BOX. The radiation-induced transconductance degradation in top-isolated devices is attributed to the increased resistance of the portion of the channel that underlies the source/drain spacers. [ABSTRACT FROM AUTHOR]

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current–voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al2O3 gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage Vth shifts and subthreshold stretchout (SS), indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and Id – Vgs measurements from cryogenic to high temperatures show the important role of defects in the Al2O3 gate dielectric to the TID response. Radiation-induced-hole trapping is attributed to oxygen vacancies in the Al2O3. The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near-interfacial Al2O3. Analysis of the temperature dependence of Vth and SS suggests that the rate at which electrons leave the Al2O3 during a positive-to-negative gate-bias sweep is higher than the rate at which they enter during a negative-to-positive gate-bias sweep. [ABSTRACT FROM AUTHOR]

Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/ ${f}$) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/ ${f}$ noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process. [ABSTRACT FROM AUTHOR]

We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS fin field-effect transistors (FinFETs) with a modified gate-stack irradiated with 10-keV X-rays under different gate biases. This modified InGaAs nMOS FinFET process shows decreased subthreshold leakage current and increased hysteresis in as-processed devices, and reduced hole trapping in irradiated devices, than first-generation development-stage devices. The reduction in subthreshold leakage current is attributed to changing the buffer layer from GaAs to In0.3Ga0.7As, thereby enhancing the material quality. Both the increased hysteresis in as-processed devices and reduced hole trapping in irradiated devices are attributed primarily to thinning the Al2O3 layer that separates the HfO2 from the InGaAs layers. This facilitates charge exchange with defects at the HfO2/Al2O3 interface and reduces the percentage of radiation-induced holes that are generated in Al2O3 and trapped in HfO2. The removal of a tungsten layer above the TiN gate reduces the interface dose enhancement. [ABSTRACT FROM AUTHOR]

The radiation hardness of AlGaN/GaN high-electron-mobility transistors (HEMTs) is found to improve with increasing GaN channel thickness. Epitaxial MgCaO shows promise as a radiation-tolerant gate dielectric, with only small shifts in operating parameters of metal–oxide–semiconductor HEMTs observed at doses up to 1 Mrad(SiO2). Bias-induced electron trapping and radiation-induced-hole trapping can occur in the MgCaO, depending on the applied bias during stress and/or irradiation. AC transconductance measurements are used to help understand charge trapping in these devices. [ABSTRACT FROM PUBLISHER]

Single-event transient (SET) responses are compared for floating-body contact, T-gate body-contact (TB), and tunnel-diode body-contact (TDBC) silicon-on-insulator (SOI) MOSFETs. The influence of three body-contact schemes on SET sensitivity is examined via irradiations as functions of position, bias voltage, and device size. The mechanisms of SET in SOI devices are discussed. Although both TB and TDBC schemes suppress floating body effects (FBEs), the TDBC scheme has superior SET hardness because it effectively eliminates charge enhancement due to bipolar amplification originating from FBEs. Thus, TDBC-structure SOI devices can lead to improved single-event upset hardness in static random access memory cells. [ABSTRACT FROM PUBLISHER]

A tunable wavelength laser system and high-resolution transient capture system are introduced to characterize transients in high-mobility MOSFETs. The experimental configuration enables resolution of fast transient signals and new understanding of charge collection mechanisms. The channel layer is critical in the charge collection process for the InGaAs FinFETs examined here. The transient current mainly comes from the channel current, due to shunt effects and parasitic bipolar effects, instead of the junction collection. The charge amplification factor is found to be as high as 14, which makes this technology relatively sensitive to transient radiation. The peak current is inversely proportional to the device gate length. Simulations show that the parasitic bipolar effect is due to source-to-channel barrier lowering caused by hole accumulation in the source and channel. Charge deposited in the channel causes prompt current, while charge deposited below the channel causes delayed and slow current. [ABSTRACT FROM PUBLISHER]

We have characterized the total ionizing dose response of strained Ge p MOS FinFETs built on bulk Si using a fin replacement process. Devices irradiated to 1.0 Mrad(SiO2) show minimal transconductance degradation (less than 5%), very small \text {V}_{th} shifts (less than 40 mV in magnitude) and very little ON/OFF current ratio degradation (<5%), and only modest variation in radiation response with transistor geometry (typically less than normal part-to-part variation). Both before and after irradiation, the performance of these strained Ge p$ MOS FinFETs is far superior to that of past generations of planar Ge $p$ MOS devices. These improved properties result from significant improvements in processing technology, as well as the enhanced gate control provided by the strained Ge FinFET technology. [ABSTRACT FROM PUBLISHER]

The effects of total-ionizing-dose irradiation are investigated in HfO2/InGaAs quantum-well MOSFETs. Radiation-induced hole trapping is higher for irradiation under positive gate bias than under negative gate bias. Electrical stress-induced electron trapping compensates radiation-induced hole trapping during positive gate-bias irradiation. Stress-induced hole trapping adds to the effects of radiation-induced hole trapping under negative gate bias. Radiation-induced charge trapping increases with the channel length. [ABSTRACT FROM PUBLISHER]

Total ionizing dose (TID) effects in ultra-thin body Ge on Insulator (GOI) junctionless CMOSFETs with recessed source/drain and channel have been studied. 10-keV X-ray irradiation leads to net hole trapping at the top and bottom Ge/dielectric interfaces of both GOI NFETs and PFETs. The Ge channel thickness and post-oxidation processing can strongly affect the radiation response. Application of negative back-gate bias can moderate the radiation-induced threshold-voltage shifts. [ABSTRACT FROM PUBLISHER]

Epitaxially grown La-based oxide has shown promise as a gate dielectric for GaAs substrate materials with a low interface trap density in the mid to low 10^11 cm ^\mathrm -2 eV ^\mathrm -1 range. Total ionizing dose (TID) effects have been studied on GaAs MOSFETs with Al2O3/La2O3 and Al2O3/La1.8Y0.2O3 gate oxides. Charge trapping mechanisms in GaAs MOSFETs are studied by the AC transconductance dispersion method. Al2O3/La2O3 gated devices show a combination of electron and hole trapping, whereas Al2O3/La1.8Y0.2O3 gated devices show primarily hole trapping. [ABSTRACT FROM PUBLISHER]

Charge collection mechanisms are investigated in surface channel GaAs MOSFETs under broadbeam heavy ion irradiation and pulsed two-photon-absorption laser irradiation. The large barrier between the gate dielectric and GaAs eliminates gate conduction current, but there is significant gate displacement current. Charge enhancement occurs because radiation-generated holes accumulate in the substrate, which increases the local electrostatic potential. The increased potential enhances the source-to-drain current, resulting in excess collected charge. The collected charge increases significantly with gate bias, due to the long tails of the charge waveforms that occur for higher gate bias. The collected charge increases with increasing drain bias. [ABSTRACT FROM PUBLISHER]

Single-event transients in SiGe MOS devices with ultrathin quantum well channels have been shown in previous work to exhibit opposite polarities for source and drain strikes. This work reports polarity reversal in similar devices with thick Ge channels due to the favorability of prompt hole collection by either the source or drain region, depending on the strike location. A slower charge-collection mechanism is also present due to the n-well/p-substrate structure, which allows ion-generated carriers from the substrate to flood the body of the device. [ABSTRACT FROM PUBLISHER]

Simulations of the SEB hardness of power MOSFETs are carried out with an experimentally calibrated structure. The effects of incorporating high permittivity gate dielectric layers and increasing channel doping concentration are investigated. The simulation results indicate that high-k dielectrics and high channel doping are promising methods to achieve SEB-hardened power MOSFETs. This offers a potential path to power MOSFETs that are resistant to SEB with thinner, more radiation-tolerant gate dielectrics. [ABSTRACT FROM PUBLISHER]

InGaAs nanowire (NW) gate-all-around (GAA) MOSFETs exhibit superior radiation hardness compared to planar devices and FinFETs, benefitting from reduced gate-oxide electric fields. Applied gate bias during irradiation, channel thickness, and presence or absence of a forming gas anneal can strongly affect NW device radiation hardness. Low-frequency noise measurements are carried out to probe near-interfacial oxide-trap (border-trap) densities, and TCAD simulations are performed to assist in understanding the charge trapping in NW channel devices with high-k gate dielectrics. Optimized device structures exhibit high radiation tolerance. [ABSTRACT FROM PUBLISHER]

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms. [ABSTRACT FROM PUBLISHER]

Single and multiple-event upsets in \ HfO_2/\ Hf one transistor, one resistor (1T1R) resistive random access memory (RRAM) structures are modeled dynamically using 3-D technology computer-aided design (TCAD) simulations. A dynamic single-event compact model is presented that allows direct correlation of the ion-generated voltage transient across the RRAM and the change in RRAM resistance. Experiments and modeling demonstrate an exponential relationship between the susceptibility of the RRAM and the applied voltage. Two implementations of the model are also presented including hardening voltage-susceptible resistive memory technologies and the impact of highly scaled access transistors. [ABSTRACT FROM PUBLISHER]

Tunnel-Diode Body-Contact (TDBC) SOI MOSFETs utilize a shallow source and a deep drain to eliminate total-ionizing-dose induced back-channel leakage and to suppress floating body effects. In contrast, significant leakage current is observed in T-gate Body-Contact (TB) SOI nMOSFETs, as a result of trapped charge in the buried oxide. A subthreshold hump is observed in TDBC SOI nMOSFETs after irradiation. The charge trapped at the shallow trench isolation (STI) corner is the major reason for the post-irradiation hump in the current-voltage characteristics. Pocket p^ + implantation reduces the size of the subthreshold hump in short-channel TDBC devices. [ABSTRACT FROM PUBLISHER]

The total-dose radiation tolerance of 32-nm nFETs is investigated. nFETs built in 32-nm RF-CMOS-on-SOI technology with high-k dielectrics show increased off-state leakage current and electron trapping in the gate oxide. The impact of CMOS-on-SOI technology scaling (from 65-nm to 32-nm) on the total-dose radiation tolerance and hot-carrier reliability (HCR) is investigated through both experiments and supporting TCAD simulations. The 32-nm nFETs exhibit less total-dose degradation compared to 45-nm nFETs. However, the hot-carrier degradation increases as the technology scales. An interplay of electric-field in the gate oxide and impact ionization in the channel region is responsible for the observed differences in the degradation mechanisms for the three technologies. [ABSTRACT FROM AUTHOR]

The temperature dependence of the low-frequency noise of 4H-silicon carbide (SiC) MOSFETs with nitrided oxides is reported over the temperature range 85–510 K. The 1/f noise decreases significantly with increasing measurement temperature. This decrease in noise results primarily from a decrease in the density of interface traps at increasing temperatures. The 1/f noise is also characterized after total ionizing dose irradiation and postirradiation annealing. No significant change in the 1/f noise is observed after the devices are irradiated to 1 Mrad (SiO2) and then annealed under bias at elevated temperature. These results show that the 1/f noise in 4H-SiC MOSFETs is dominated by the interaction of channel carriers with slow interface traps at temperatures <360~K and with border traps >\rm\!360~K. This result contrasts with most experience with Si/SiO2-based MOSFETs, and results from the wider bandgap and greater density of slow interface traps in SiC/SiO2-based MOSFETs than in Si/SiO2-based MOSFETs. [ABSTRACT FROM AUTHOR]

Irradiated Ge pMOSFETs have been characterized via charge pumping (ICP) and 1/f noise. The noise increases much more with irradiation than does ICP for devices with eight Si monolayers at the interface, while devices with five Si monolayers and lower halo implantation dose exhibit comparable increases in noise and ICP with irradiation. These results suggest that border traps in the HfO2 affect the noise more than interface traps, and that devices with eight Si monolayers have a higher border-trap density than devices with five Si monolayers. Noise measurements as a function of gate voltage show that the border trap density increases significantly toward the Ge valence band edge, while three-level charge pumping reveals an interface trap density that increases slightly toward midgap. [ABSTRACT FROM AUTHOR]

The total ionizing dose response of triple-gate MOSFETs is investigated for various fin widths and bias conditions. Experiments and simulations are used to analyze the buildup of trapped charge in the buried oxide and its impact on the threshold-voltage shift and subthreshold-slope degradation. The higher total-dose tolerance of multiple-gate FinFETs with narrow fins is attributed to lateral gate control over the electrostatic potential in the body and especially at the Si fin/BOX interface. It is demonstrated that ON-state irradiation is the worst-case bias configuration for triple-gate MOSFETs through extensive experimental analysis. [ABSTRACT FROM PUBLISHER]

The irradiation and annealing responses of Ge pMOSFETs have been investigated under transmission gate bias. Both the radiation-induced charge trapping and the low frequency (1/ f ) noise increase with total ionizing dose and decrease with annealing time. The smallest increases in noise after irradiation are observed for Ge pMOSFETs with the lowest halo implantation doses. The smallest increases in oxide and interface trap charge densities are obtained for devices with eight monolayers of Si at the interface, as compared to devices with five Si monolayers. [ABSTRACT FROM AUTHOR]

The irradiation and annealing responses of Ge pMOSFETs are investigated as a function of device processing. Transmission gate bias is found to be the worst-case irradiation bias condition. Junction leakage increases with total dose, which leads to a decrease in the I on /I off ratio. The I on /I off ratio recovers with room temperature annealing. Both band-to-band tunneling and trap-assisted tunneling contribute to the observed leakage. Device leakage before and after irradiation is found to be sensitive to halo implant dose and the number of Si monolayers at the Ge/insulator interface. Interface trap densities and body leakage also increase with dose and decrease with annealing. [ABSTRACT FROM AUTHOR]

We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T-DRAM cells programmed with back-gate pulses are quite sensitive to total ionizing dose radiation, with the memory sensing margin and retention time decreasing significantly with increasing dose. In contrast, the sensing margin and retention time show high tolerance to total ionizing dose irradiation when the 1T-DRAM cells are programmed via GIDL. The sensing margin increases significantly with decreasing gate length for 1T-DRAM cells programmed via GIDL. We conclude that capacitor-less 1T-DRAMs programmed via GIDL are strong candidates for embedded memory applications for ultimately scaled CMOS devices in high-TID applications. [ABSTRACT FROM AUTHOR]

The effects of shallow-trench-isolation-induced mechanical stress on radiation-induced off-state leakage current are reported in 90-nm NMOS devices. The radiation-induced leakage current increases with increasing active device-to-isolation spacing. The leakage current also depends on channel width; narrow devices exhibit less leakage before irradiation, but more after irradiation. These geometrical factors affect the mechanical stress in the device, which impact the dopant diffusion and activation and the charge trapping in the STI oxide. The combined effects of these layout-related phenomena affect the sensitivity to radiation-induced charge. [ABSTRACT FROM AUTHOR]

Detailed studies of the temperature and voltage dependences of the low-frequency noise of 4H-SiC MOSFETs and TCAD simulations show that the noise is caused primarily by interface traps. First-principle calculations identify these traps as carbon vacancy clusters and nitrogen dopant atoms at or near the \SiC/SiO2 interface. [ABSTRACT FROM AUTHOR]