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Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]

Positive charges (PCs) in gate dielectric shift the threshold voltage and cause a time-dependent device variability. To assess their impact on circuits, it is useful to know their distribution for a wide energy range both within and beyond silicon bandgap. Such a distribution is still missing, and a technique for its extraction has not been demonstrated yet. The central objective of this paper is, for the first time, to develop a new fast technique and to demonstrate its capability for probing the energy distribution of PCs over such a wide energy range. Results show that PCs can vary significantly with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps that are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence-band edge are from created defects. The PCs within the bandgap have a peak near Ev + 0.8 eV and saturate for either longer stress time or higher stress temperature. In contrast, the PCs above a conduction band edge, namely the antineutralization positive charges, do not saturate, and their generation is clearly thermally accelerated. [ABSTRACT FROM AUTHOR]

Defects in gate oxide cause breakdown and shorten device lifetime. Early works mainly focused on generation process that converts a precursor into a charged defect. Although it can be neutralized through “recovery,” the defect is still there and will recharge when resuming stress. Recently, we have shown that this is not always the case and some defects can be lost, but a detailed investigation is missing. The central objective of this work is to accurately define and extract the loss, separate it from slowdown, and evaluate their enhancement of device lifetime. Loss is defined as elimination of defects, while slowdown means that recharging a “hardened” precursor takes longer than charging a fresh one. Clear evidences show that losses originate from permanent components, i.e., generated interface states and antineutralization positive charges, while slowdown occurs to both permanent and recoverable components. Loss is thermally accelerated, but slowdown of recoverable component is not. This improved understanding adds slowdown and losses to the existing framework for defects. For the first time, we report that the losses and slowdown enhance device lifetime by a factor of 2.6–4.3, for an allowed threshold voltage shift of 20–45 mV. [ABSTRACT FROM AUTHOR]

As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an inverter and competing with the MOSFET. We have investigated the heterostructure TFET with respect to complementarity based on our semianalytical model, and we propose the In~Ga1~As-source silicon-TFET as p-TFET. This design is partitularly applicable to nanowire-based transistor architectures. We discuss the complementarity of the I-V curves, and we analyze the threshold voltage behavior of the complementary TFETs. [ABSTRACT FROM AUTHOR]

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The loca- tion of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiONIIL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, posi. tive charges cannot be reduced by using a thinner HfSiON film. Index Ternzs-Hf silicates, high-k gate dielectric, instability, negative bias temperature instability (NBTI), positive charges, reliability, spatial distribution. [ABSTRACT FROM AUTHOR]

This paper shows important improvements in charge pumping (CP) measurements on stacked high-k dielectrics, where the defects in high-k and SiO2 can be distinguished and estimated. The spatial profile of the interface traps and bulk traps is obtained by plotting the trap density as a function of the discharge time. Furthermore, the spectroscopic character of the base-level CP technique is demonstrated in HfSiON/SiO2 gate dielectrics by changing the applied pulse bias. It is found that when large pulse amplitude is applied to the gate, two bands appear superimposed on top of the usual base-level CP curve, suggesting the presence of two separate defect energy levels in the high-k dielectric. [ABSTRACT FROM AUTHOR]

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability ΔVth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates ΔVth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of ΔVth is clarified. [ABSTRACT FROM AUTHOR]

The effects of source/drain activation thermal bud- get and premetallization degas conditions on interfacial re- growth, carrier mobility, and defect densities are examined for SiO2/HfO2/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-κ bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 °C spike for t = 1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 °C for t = 60 s). For 1000 °C spike-annealed films, where the highest SiO2/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO2 and the IL which increases for high-temperature processing. [ABSTRACT FROM AUTHOR]

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Å, a leakage current of 1.5 A/cm² at VG = 1 V, a peak mobility of 190 cm²/V · s, and a drive-current of 815 μA/μm at an OFF-state current of 0.1 μA/μm for VDD = 1.2 V. Identical gate stacks processed with a 1000-°C spike anneal have a higher peak mobility at 275 cm²/V · s, but a 5-Å higher EOT and a reduced drive current at 610 μA/μm. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 °C) for a ten-year lifetime, whereas positive-bias temperature-instability :measurements indicate a sufficient lifetime for operating voltages below 0.75 V. [ABSTRACT FROM AUTHOR]

Dielectric relaxation currents in SiO2 /Al2O3 and SiO2 /HfO2 high-κ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-κ dielectric stacks. It is found that high-κ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-κ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO2/high-κ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO2/high-κ interface is a key requirement for high-κ dielectric stack application and reliability in MOS devices. [ABSTRACT FROM AUTHOR]

The energy band-alignment of a multimetal-layer gated metal-oxide-semiconductor structure is investigated. An analytical expression for the Fermi level of the metal stack is derived. It is shown that the thin metal layer contacting the gate dielectric plays a critical role in determining the work function of the whole metal stack, in agreement with experimental results. [ABSTRACT FROM AUTHOR]

The article discusses the means of improving the workfunction control of metal gate electrodes. The author cites that the key challenge for applying metal gates for metal-oxide-semiconductor field-effect transistor is the choosing of a metal with suitable workfunction. The author also defines a novel route to workfunction control through the alteration of the interface polarization layer by cautious deposition of dielectric stack and metal gate, then, by a temperature treatment.