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In this paper, we report an experimental observation of the two-stage turn-on characteristic in normally-OFF Al2O3/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) on Si substrate. The impact of oxide/GaN interface traps with different energy levels on the switching behavior of the device was extensively examined by simulation and verified by measurements. The interface traps at 0.4 eV below the bottom of the conduction band (Eit = EC-0.4 eV) of GaN buffer with a density of Dit = 6.5 x 1012 cm-2 was identified responsible for the ob- served two-stage turn-on characteristic. The weak Fermi-level pinning (WFLP) induced by the dynamic electron filling of interface traps may hamper the electron from accumulating in the Al2O3/GaN MOS-channel and then manifests a premature turn-on during the switching-on process. [ABSTRACT FROM AUTHOR]

A novel low specific on-resistance (Ron,sp) lateral double-diffused metal oxide semiconductor (LDMOS) with a buried improved super-junction (BISJ) layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage (BV). The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively. [ABSTRACT FROM AUTHOR]

A strained-SiGe p-channel metal-oxide-semiconductor-field-effect transistors (p-MOSFETS) with higher-κ LaLuO3 gate dielectric was fabricated and electrically characterized. The novel higher-κ (κ∼30) gate dielectric, LaLuO3, was deposited by molecular-beam deposition and shows good quality for integration into the transistor. The transistor features good output and transfer characteristics. The hole mobility was extracted by the splitting C—V method and a value of 200cm2/V·s was obtained for strong inversion conditions, which indicates that the hole mobility is well enhanced by SiGe channel and that the LaLuO3 layer does not induce additional significant carrier scattering. Gate induced drain leakage is measured and analyzed by using an analytical model. Band-to-band tunneling efficiencies under high and low fields are found to be different, and the tunneling mechanism is discussed. [ABSTRACT FROM AUTHOR]

In this article, silicon on insulator (SOI) was fabricated by separation by implanted oxygen (SIMOX) layer transfer process. The thickness uniformity of the top Si (superficial Si of the SOI) evaluated by spectroscopic ellipsometry remains constant through the etch-stop thinning process. A defect-free top Si was observed by transmission electron microscopy, as well as its atomic-scale sharp interface that was adjacent to the buried oxide (BOX) layer. The top Si/BOX interface properties, including upper BOX surface roughness and interface state density, were investigated by atomic force microscopy (AFM) and pseudo-metal-oxide-semiconductor method, respectively. In addition, the surface morphology of the square pit and square hole defect of the top Si were observed. Using AFM, it is found that the morphology depends on the top Si/BOX interface morphology of the donor wafer and can be improved by optimizing the annealing process. The square hole defect caused by anisotropic etching is discussed in detail, and it is proven to originate from the defects in the SIMOX BOX. [ABSTRACT FROM AUTHOR]

Abstract-A new superjunction LDMOS on silicon-on-insulator (SOl) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the highdensity oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (By). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to 6 x 10[sup6] V/cm, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 μm and drift length of 15 μm on a thin SO! substrate. [ABSTRACT FROM AUTHOR]

Focuses on a study that discussed the experimental verification of the metal oxide semiconductor (MOS)-controlled diode (MCD) key concept by using commercially available power MOS field effect transistors operating as MCD. Information on MCD; Theory and operation principle of the MCD; Expected MCD performance; Experimental demonstration; Conclusions.

A novel silicon controlled rectifier (SCR) with high holding voltage ( for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (, the two SCRs are turned on at the same time to induce the first snapback with high (. As the increases, the SCR2 will be turned off because of its low current gain. Therefore, the will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high (. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized of 7.4 V with a maximum failure current ( of 14.7 mA/ is obtained by the simulation. [ABSTRACT FROM AUTHOR]

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer. [ABSTRACT FROM AUTHOR]

A low specific on-resistance SOI LDMOS with a novel junction field plate (JFP) is proposed and investigated theoretically. The most significant feature of the JFP LDMOS is a PP—N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buried oxide layer (BOX) and thus widens the vertical conduction area. As a result, the breakdown voltage (BV) is improved and the specific on-resistance (Ron,sp) is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ·cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices. [ABSTRACT FROM AUTHOR]

An analysis model of the dV/dt capability for a metal—oxide—semiconductor (MOS) controlled thyristor (MCT) is developed. It is shown that, in addition to the P-well resistance reported previously, the existence of the OFF-FET channel resistance in the MCT may degrade the dV/dt capability. Lower P-well and N-well dosages in the MCT are useful in getting a lower threshold voltage of OFF-FET and then a higher dV/dt immunity. However, both dosages are restricted by the requirements for the blocking property and the forward conduction capability. Thus, a double variable lateral doping (DVLD) technique is proposed to realize a high dV/dt immunity without any sacrifice in other properties. The accuracy of the developed model is verified by comparing the obtained results with those from simulations. In addition, this DVLD MCT features mask-saving compared with the conventional MCT fabrication process. The excellent device performance, coupled with the simple fabrication, makes the proposed DVLP MCT a promising candidate for capacitor discharge applications. [ABSTRACT FROM AUTHOR]