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We report a mechanically enhanced inkjet-printed microelectromechanical (MEM) relay with a U-bar-shaped cantilever by exploiting the coffee-ring effect. The printed cantilever shape, especially the effective thickness caused by the elevated walls, can be controlled during the drying process by outward convective flow of silver nanoparticles. This enhances mechanical stiffness to efficiently produce a strongly suspended cantilever that is immune to collapse- and curling-related failures. This approach to enhancing cantilever stiffness is unique to printing-based processes using metalnanoparticle inks and is not feasible for conventional photolithography processes. The resulting printed MEM relays show a pull-in voltage of only 6.6 V and an on/off ratio of 108 with extremely low on-state resistance (~14.3 Ω) and off-state leakage that is comparable to those of conventional silicon-based MEM relays. [ABSTRACT FROM AUTHOR]

Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage (Vdd) and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy–delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2 \times energy increase can be traded off for a \sim\!\!\1.5\times reduction in relay delay. A contact-gap-to-actuation-gap thickness ratio of 0.7–0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide >\10\times energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to \sim100 MHz. [ABSTRACT FROM AUTHOR]

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area. [ABSTRACT FROM AUTHOR]

Four-terminal-relay inverter circuit characteristics are investigated. To achieve maximum noise margin and zero crowbar current while allowing for relay-to-relay variations, the optimal biasing scheme provides for switching that is symmetric about VDD/2 with minimum hysteresis and no possibility of both the pull-down and pull-up devices being on simultaneously. [ABSTRACT FROM AUTHOR]

Various logic functions can be implemented by appropriately biasing a single seesaw relay. The seesaw relay can also be configured as a bistable latch so that a memory cell can be implemented with one relay and one access transistor. Measurements of seesaw relay switching speed are well matched to lumped-parameter modeling results. [ABSTRACT FROM AUTHOR]

A dual-ended ("seesaw") relay design is proposed for ultralow-power digital logic applications. Fabricated seesaw relays demonstrate a perfectly complementary switching behavior that is symmetric about VDD/2, with extremely steep switching behavior (< 0.1 mV/dec) and low ON-state resistance (< 1 kΩ). The perfectly complementary and symmetric operation provides for maximum operating voltage margin and minimal crowbar current, as evidenced by an abrupt inverter voltage transfer characteristic. [ABSTRACT FROM AUTHOR]