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Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic.
- Source :
- IEEE Transactions on Electron Devices; 01/01/2011, Vol. 58 Issue 1, p236-250, 15p
- Publication Year :
- 2011
-
Abstract
- Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage (Vdd) and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy–delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2 \times energy increase can be traded off for a \sim\!\!\1.5\times reduction in relay delay. A contact-gap-to-actuation-gap thickness ratio of 0.7–0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide >\10\times energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to \sim100 MHz. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 58
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 57254073
- Full Text :
- https://doi.org/10.1109/TED.2010.2082545