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In this article, a 0.7 nm thick monolayer MoS2 nanosheet gate-all-around field effect transistors (NS-GAAFETs) with conformal high- κ metal gate deposition are demonstrated. The device with 40 nm channel length exhibits a high on-state current density of ~410 μ A μ m−1 with a large on/off ratio of 6 × 108 at drain voltage = 1 V. The extracted contact resistance is 0.48 ± 0.1 kΩ μ m in monolayer MoS2 NS-GAAFETs, thereby showing the channel-dominated performance with the channel length scaling from 80 to 40 nm. The successful demonstration of device performance in this work verifies the integration potential of transition metal dichalcogenides for future logic transistor applications. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

Conventional junctionless (JL) multi-gate (MuG) field-effect transistors(FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. [ABSTRACT FROM AUTHOR]

Abstract Internal photoemission of electrons from uncapped monolayer graphene to insulating SiO 2 has been observed in samples prepared by water-intercalation based graphene transfer. The barrier height between the graphene Fermi level and the oxide conduction band bottom was reproducibly found to be 4.1–4.2 eV. Moreover, this value was weakly sensitive to the contacting metal work function (Al, Cu, Au). This barrier height corresponds to an effective work function of graphene close to 5.0 eV, which is nearly 0.5 eV higher than the usually reported vacuum value. Highlights • Internal photoemission of electrons has been detected from uncapped monolayer graphene. • Effective work function (EWF) of graphene has been determined to be 5.0 eV. • EWF of graphene at the interface with SiO 2 is 0.5 eV higher than the vacuum value. [ABSTRACT FROM AUTHOR]