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In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed based on a charge-based model. Interface charge traps arising from exposure to chemicals, high-energy ionizing radiation, or aging mechanism could degrade the charge–voltage characteristics. The model is predictive in a range of temperatures from 77 to 400 K. The validity of the approach is confirmed by extensive comparisons with numerical technology computer-aided design (TCAD) simulations in all regions of operation from deep depletion to accumulation and from linear to saturation. [ABSTRACT FROM AUTHOR]

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency (${g}_{\textsf {m}}/{I}_{\textsf {D}}$) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency (${y}_{\textsf {m}}/{I}_{\textsf {D}}$) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$. [ABSTRACT FROM AUTHOR]

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET. [ABSTRACT FROM AUTHOR]

Transconductance efficiency ( gm/{I}D ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of gm/{I}D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the gm/{I}D -based design methodologies usage in DG FDSOI transistors sizing. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new method to extract the free carrier mobility in junctionless (JL) double-gate FETs biased in accumulation. We show that, in addition to assuming a well-defined field-dependent mobility law, using the well-known $Y$ -function is not accurate enough in JL FETs. In addition, the new methodology is also interesting for inversion-mode FETs. This approach has been assessed with technology computer-aided design simulations, and confirms its robustness both for JL and inversion-mode devices. [ABSTRACT FROM PUBLISHER]

This paper presents analytical expressions for channel noise, induced gate noise (IGN), and cross-correlation noise in a long-channel junctionless (JL) double-gate MOSFET. The analytical relationships, which have been derived from a coherent charge-based model, are validated with technology computer-aided design simulations, and the figures of merit have been compared with the inversion mode FETs. For a given current, we found that the channel thermal noise is very similar for both architectures, whereas the IGN is slightly decreased in the JL FETs. [ABSTRACT FROM AUTHOR]

In this paper, we present an analytical semiempirical model of the profile of the channel charge and potential in quasi-ballistic double-gate (DG) MOSFETs. The charge model is based on the premise of separating the charge density in the quasi-ballistic channel into two hypothetical components: 1) exclusively ballistic (collision-free) and 2) collision-dominated components, which are governed by the same electrostatics. These components are related to each other through a ballisticity parameter whose values lie between 0 and 1. Varying the value of this parameter allows us to model the charge profile continuously between diffusive and purely ballistic devices. Using the proposed charge model and the DG MOSFET electrostatics, an analytical expression for the channel potential is derived which, like the charge model, is continuous between the diffusive and ballistic regimes. [ABSTRACT FROM AUTHOR]

We have developed a closed-form solution for trans-capacitances in long-channel junctionless double-gate (JL DG) MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with technology computer-aided design simulations. According to this paper, a complete intrinsic capacitance network is obtained, which represents an essential step toward ac analysis of circuits based on junctionless devices. [ABSTRACT FROM PUBLISHER]

In this paper, we present an analytical noise modeling methodology for lateral nonuniform MOSFET. We demonstrate that the noise properties of lateral nonuniform MOSFETs are considerably different from the prediction obtained with the conventional Klaassen-Prins (KP)-based methods which, at low gate voltages, depending on the doping profile can overestimate the thermal noise by 2-3 orders of magnitude. We show that the presence of lateral nonuniformity makes the vector impedance field (the quantity responsible for noise propagation) position and bias dependent. This insight clearly explains the observed discrepancy and shows that the bias dependence of the important noise parameters cannot be predicted by conventional KP-based methods. [ABSTRACT FROM AUTHOR]

The Ward-Dutton (WD) partitioning scheme [IEEE Trans. Electron Devices, vol. ED-27, p. 1571, Aug. 1980] is used extensively to develop transient and high-frequency advanced compact models for MOSFET devices. Recently, it has been shown that WD partitioning fails for field-dependent mobility [IEEE Electron Device Lett., vol. 27, p. 674, Aug. 2006] or for laterally asymmetrical doping [IEDM Tech. Dig., p. 751, Dec. 2004], [IEEE Trans. Electron Devices, vol. 53, p. 270, Feb. 2006]. This paper is aimed at presenting a generalization of the partitioning concept. We show that, although it is not possible to guaranty a partitioning scheme for general operation of the MOSFET, it is possible to show the existence of a partitioning scheme for small-signal operation of the device accounting for both field-dependent mobility and lateral asymmetry. Application of this new concept in capacitance evaluation of lateral asymmetric MOSFET considerably simplifies the existing capacitance-evaluation methodology and accounts for any arbitrary field-dependent mobility. It also gives a mean to physically understand the unusual behavior of Cdg in lateral asymmetric MOSFET. We also show how failure of the WD partitioning can affect the present compact-modeling methodologies. [ABSTRACT FROM AUTHOR]

Abstract: We propose a design oriented charge-based model for undoped DG MOSFETs under symmetrical operation that aims at giving a comprehensive understanding of the device from the design strategy. In particular, we introduce useful normalizations for current and charges that in turn lead to very simple relationships among the physical quantities. Finally, we emphasize on the link that exists between this approach and the EKV formalism derived for bulk MOSFETs, which in turn leads to the unique g ms/I D design methodology for DG architectures. [Copyright &y& Elsevier]

We propose an analytical model that accounts for SRH generation and recombination rates in both the depletion and the neutral regions inherent to the channel of bulk and PD-SOI MOSFETs. Unlike earlier approaches, this model is valid in all modes of operation, from weak to strong inversion and from conduction to saturation and also includes the contribution from the neutral substrate. Moreover, we demonstrate that all the quantities are simply expressed as the product of a normalization factor times a normalized function that only depends on the DC operating point, thus leading to a simple and efficient formulation of SRH rates. Compared with 2D numerical simulations, the model predictions show an excellent agreement for a broad range of trap parameters. Finally, the limit of validity of the present approach is addressed in details. [Copyright &y& Elsevier]

In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations. [Copyright &y& Elsevier]