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Biosensor-based devices are undergoing continuous advances in technology and design. Many studies on biosensor-based tunnel field-effect transistors have recently been published, but none of them has discussed the effect of the dual-drain technique with regard to the sensitivity of nanowire tunnel field-effect transistor-based biosensors. In this work, the role of a dual drain is investigated with respect to both the sensitivity and linearity performance of the device. To cover a vast range of enzymes, the permittivity of the cavities was varied from κ = 3 to κ = 25, and it was observed that a dual drain resulted in 85- and 2000-fold improved sensitivity, respectively. Along with the investigated nanowire, a sensitivity comparison with previous devices was carried out, which showed that for all the devices, the dual-drain technique significantly enhanced sensitivity; hence, in the future, this investigated technique can be used for improved sensing in biomedical devices. [ABSTRACT FROM AUTHOR]

In this paper, a source delta-doped vertical nanowire tunnel field-effect transistor is proposed, and its 2D simulations using the Silvaco ATLAS TCAD tool for ultralow-power applications are investigated. Because electron tunneling occurs in a direction parallel to the electric field at the source/channel interface, the ON-state current is higher. By incorporating a delta-doped layer in the source area, the OFF-state leakage current is further reduced. For various electrical parameters, the effects of changing the position of the delta-doped layer is investigated, as well as the effect of changing the doping concentration of the delta-doped layer and the device gate work function. It was possible to achieve a very high current ratio (ION/IOFF) of order ~ 1011 (with ION value 1.52 × 10–5 A/µm) with a very low average subthreshold slope of 18 mV/decade, and threshold voltage (VTH) of 0.57 V. [ABSTRACT FROM AUTHOR]

As we know that technology is improving day by day, due to this the number of transistors on chip should be doubled every year as per "Moore's Law". Hence, the size of transistor should be reduced to follow this scaling trend but using conventional planar MOSFET we cannot reduce the size of transistor to a limit. This is happened because of short channel effects (SCEs), which degrades MOSFET performance at lower dimensions. But there are many alternate structures like nanotube, nanowire, graphene etc. which will help in reducing the size of transistor by offering lower SCEs. In this paper, we will discuss about various types of nanowire MOSFETs and their analog performances like ION, IOFF, ION/IOFF current ratio. Beside this, an in depth review of doping control issues and the possible solutions in the nanowire MOSFETs are also presented. [ABSTRACT FROM AUTHOR]

In this reported work, we have analyzed the different figure of merits for dopingless TFET. The charge-plasma based Planar-TFET does have a dual-gate with a half structure made from Silicon–Germanium (Si–Ge) compound. The Si–Ge is used with a composition factor of 0.45. The Si0.55Ge0.45 helped in the current enhancement of the Silicon-based TFET device. Several linearity parameters are calculated for low and high drain bias to acknowledge the device behavior at different biasing conditions. The heteromaterial planar-TFET is optimized according to the physical conditions where the source contact is considered as Schottky contact with barrier lowering. The work function of the source electrode is varied to check the effects of the Schottky barrier on the device characteristics. The optimized dopingless TFET is scaled down to lower dimensions for the possibility of nano-TFET devices without compromising the device performance. The nanoscaled dopingless nanowire TFET performs better as compared to dopingless planar TFET with similar dimensions. The obtained cutoff frequency is greater than 10 GHz and intermodulation distortion is less than − 650 dBm. The optimized structure showed low noise and harmonic distortions to be used for better sensing applications. [ABSTRACT FROM AUTHOR]

In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel–surround gate–oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs. [ABSTRACT FROM AUTHOR]

In this paper, a gate-all-around (GAA) charge plasma-based dopingless dual material gate nanowire FET is proposed (CP-DM). This structure is further explored by adding gate-stack (high-k + SiO2) feature (CP-GS-DM). In these dopingless structures, source/drain is induced using a charge plasma concept by an appropriate selection of work functions for source/drain electrodes. The dopingless devices offer low thermal budget with easier fabrication steps and reduced random dopant fluctuations effect. Both the dopingless structures are investigated for analog performance, and results are compared with those obtained from the GAA junctionless dual material (JL-DM) gate and the JL gate-stacked DM gate (JL-GS-DM), respectively. The charge plasma-based dopingless devices when compared with their JL counterpart show improvement in drive current (${I}_{\text {D}}$), transconductance (${g}_{m}$), transconductance gain factor (${g}_{m}/{I}_{D}$), output conductance (${g}_{\text {ds}}$), early voltage (${V}_{\text {AE}}$), intrinsic gain ($A_{\text {v}}$), drain-induced barrier lowering, and subthreshold slope. Thus, dopingless structures show enhanced analog performance with reduced short channel effects. The charge plasma based dopingless gate stacked dual material gate (CP-GS-DM) shows the best performance of all the structures. The analysis is further carried out for investigating the device design parameters effect on performance, namely, total gate length, ${L}_{G}$ , and ratio of control gate length to total gate length, $L_{\text {M1}}/{L}_{G}$. This way dopingless charge plasma-based devices incorporate DM and GS features that make these devices interesting and reliable candidates for analog application with cost-effective fabrication. [ABSTRACT FROM AUTHOR]