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Inspired by the human brain, spiking neuron networks are promising to realize energy-efficient and low-latency neuromorphic computing. However, even state-of-the-art silicon neurons are orders of magnitude worse than biological neurons in terms of area and power consumption due to the limitations. Moreover, limited routing in typical CMOS processes is another challenge for realizing the fully-parallel high-throughput synapse connections compared to biological synapses. This paper presents an SNN circuit that utilizes resource-sharing techniques to address the two challenges. Firstly, a comparator sharing neuron circuit with a background calibration technique is proposed to shrink the size of a single neuron without performance degradation. Secondly, a time-modulated axon-sharing synapse system is proposed to realize a fully-parallel connection with limited hardware overhead. To validate the proposed approaches, a CMOS neuron array is designed and fabricated under a 55-nm process. It consists of 48 LIF neurons with 3125 neurons/mm 2 area density, power consumption of 5.3 pJ/spike, and equivalent 2304 fully parallel synapses providing a unit throughput of 5500 events/s/neuron. It proves the proposed approaches are promising to realize a high-throughput high-efficiency SNN with CMOS technology.

This article presents a low-power low-noise neural recording system comprising a set of 4-channel amplifiers and a dual-threshold adaptive action potential detector. The front-end amplifier is optimized for power efficiency, noise, and silicon area. A balanced tunable pseudo-resistor is used to acquire local field potential (LFP) and action potential (AP) separately. The post-layout simulation results show that the system achieved input referred noise 4.7 μVrms and noise efficiency factor (NEF) 2.79 with mid-band gain of 51.9 dB and power consumption of 5.22 μW. The bandwidth is highly tunable in the range of 2.38 Hz-300 Hz for high-pass corner and 248 Hz-12.9 kHz for low-pass corner, which can acquire AP and LPF without out-band noise. The proposed dual-threshold adaptive AP detector can capture action potential precisely from background activity, thus data reduction can be realized by only processing these significant waveforms. The results show that the proposed low-power, low-noise biomedical system is suitable for implantable device applications.

This paper presents a low-noise low-power amplifier for implantable device for neural signal acquisition. By operating MOS transistors in the subthreshold region, smaller low-frequency noise and lower power consumption can be achieved. A low power, low-noise common-drain buffer and a low-noise, high-linearity, low pass filter are used for high frequency noise filtering. Post-layout simulation shows the input referred noise of the system is 2.19microVrms from 10Hz to 10 KHz, power consumption is 55.8microW, and the NEF is 2.53. The amplifier was fabricated using a TSMC 0.18microm 1P6M CMOS process. Simulation results show that this low-noise, low-power amplifier is suitable for implantable device applications.

This brief presents a conductance-based neuron that is capable of operating under ultra-low-voltage supplies. The proposed neuron employs a variable-gain low-pass filter to linearly integrate the input spikes onto the membrane capacitance. A positive feedback topology is used to generate output spikes and implement a frequency adaption mechanism. A differential amplifier is as well employed as a comparator to reset the membrane potential and set a threshold voltage to control the spike generator circuit. The mathematical analyses result in a first-order linear equation for membrane current of the neuron. The designed neuron was fabricated in TSMC 0.18 $\mu \text{m}$ CMOS technology with an area of 993 $\mu \text{m}^{2}$ that consumes 135 fJ/spike under a 0.3-V supply voltage. The experimental results show frequency adaption mechanism and intrinsic chattering, while regular and fast-firing behaviors are achieved by adjusting control parameters. [ABSTRACT FROM AUTHOR]

Although deep brain stimulation (DBS) has been a promising alternative for treating several neural disorders, the mechanisms underlying the DBS remain not fully understood. As rat models provide the advantage of recording and stimulating different disease-related regions simultaneously, this paper proposes a battery-less, implantable neuro-electronic interface suitable for studying DBS mechanisms with a freely-moving rat. The neuro-electronic interface mainly consists of a microsystem able to interact with eight different brain regions bi-directionally and simultaneously. To minimize the size of the implant, the microsystem receives power and transmits data through a single coil. In addition, particular attention is paid to the capability of recording neural activities right after each stimulation, so as to acquire information on how stimulations modulate neural activities. The microsystem has been fabricated with the standard 0.18 \mum CMOS technology. The chip area is 7.74 mm^2, and the microsystem is able to operate with a single supply voltage of 1 V. The wireless interface allows a maximum power of 10 mW to be transmitted together with either uplink or downlink data at a rate of 2 Mbps or 100 kbps, respectively. The input referred noise of recording amplifiers is 1.16 \muVrms, and the stimulation voltage is tunable from 1.5 V to 4.5 V with 5-bit resolution. After the electrical functionality of the microsystem is tested, the capability of the microsystem to interface with rat brain is further examined and compared with conventional instruments. All experimental results are presented and discussed in this paper. [ABSTRACT FROM PUBLISHER]

Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a nose-on-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. The chip has eight on-chip sensors, an adaptive interface, a successive approximation analog-to-digital converter (SAR ADC), a learning kernel of continuous restricted Boltzmann machine (CRBM), and a RISC-core with low-voltage SRAM. The functionality of VAP identification was verified using clinical data. In total, 76 samples infected with pneumonia (19 Klebsiella, 25 Pseudomonas aeruginosa, 16 Staphylococcus aureus, and 16 Candida) and 41 uninfected samples were collected as the experimental group and the control group, respectively. The results revealed a very high VAP identification rate at 94.06% for identifying healthy and infected patients. A 100% accuracy to identify the microorganisms of Klebsiella, Pseudomonas aeruginosa, Staphylococcus aureus, and Candida from VAP infected patients was achieved. This chip only consumes 1.27 mW at a 0.5 V supply voltage. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem. [ABSTRACT FROM PUBLISHER]