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Resistance drift in phase change memory (PCM) reduces the accuracy of analog computing applications such as neural network inference. Recently, PCMs based on superlattice (SL) phase change layers have shown low resistance drift, however the origin of this low drift remains unexplored. Here, we uncover that resistance drift in SL-PCM based on alternating layers of Sb2Te3 and Ge2Sb2Te5 (GST) is controlled by the number of SL interfaces as well as the degree of SL intermixing. Temperature-dependent measurements reveal smaller and more stable activation energy upon annealing (thus suppressed structural relaxation) in our SL-PCM vs. control GST devices, accounting for the low resistance drift. By controlling SL interfaces, we achieve low resistance drift coefficient ${v} < 0.01$ in these SL-PCMs, maintained after extensive cycling and at various read voltages and intervals - showing robustness required for analog computing with PCM. [ABSTRACT FROM AUTHOR]

Large switching current density and resistance drift remain challenges for phase change memory (PCM) in data storage and neuromorphic computing applications. Here, we address these by electro-thermal and structural confinement in a GeTe/Sb2Te3 superlattice PCM (SL-PCM) with thermally-induced phase change, while observing scalability with bottom electrode diameter. We demonstrate ~ $\text{8-10}\times $ reduction of reset current density $({J}_{\text {reset}})$ and ~ $\text{25-30}\times $ reduction of power $({P}_{\text {reset}})$ in our mushroom cell SL-PCM compared to control Ge2Sb2Te5 (GST) PCM with the same device structure. The SL-PCM devices also exhibit multi-level states with $\sim 10\times $ lower resistance drift compared to control GST PCM. Material characterization and electro-thermal simulations confirm the role of heat confinement in SL-PCM, paving the way towards low-power, high-density memory and data storage. [ABSTRACT FROM AUTHOR]

High switching current density has been a key bottleneck for phase change memory (PCM) technology. Here, we demonstrate interfacial thermoelectric heating (TEH) as a promising way of tackling this challenge. We use TEH induced by a thin Bi2Te3 interfacial layer to demonstrate $\sim 2\times $ reduction of reset current density (${J} _{\text{reset}}$) and power (${P} _{\text{reset}}$) compared to control PCM devices based on Ge2Sb2Te5 (GST). Measurements of polarity-dependent reset current and power in well-cycled devices reveal the strong TEH caused by the Bi2Te3 interfacial layer. The TEH origin of ${J} _{\text{reset}}$ reduction is further confirmed by electro-thermal simulations. Such TEH-engineered PCM devices are scalable with the bottom electrode diameter and thus could be promising for high density data storage applications. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is an emerging data storage technology; however, its programming is thermal in nature and typically not energy-efficient. Here, we reduce the switching power of PCM through the combined approaches of filamentary contacts and thermal confinement. The filamentary contact is formed through an oxidized TiN layer on the bottom electrode, and thermal confinement is achieved using a monolayer semiconductor interface, three-atom thick MoS2. The former reduces the switching volume of the phase change material and yields a 70% reduction in reset current versus typical 150 nm diameter mushroom cells. The enhanced thermal confinement achieved with the ultra-thin (∼6 Å) MoS2 yields an additional 30% reduction in switching current and power. We also use detailed simulations to show that further tailoring the electrical and thermal interfaces of such PCM cells toward their fundamental limits could lead up to a sixfold benefit in power efficiency. [ABSTRACT FROM AUTHOR]

High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (D'S) of SiO2/Al2O3 insulator. Devices with contact area of 500 × 20 nm and lengths of 2 μm show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the D'S enables a 60% reduction in reset energy compared with SiO2-isolated devices. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade. [ABSTRACT FROM AUTHOR]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

Electrothermal transport and crystallization dynamics govern the speed and bit stability of multibit phase-change memory (PCM). This paper develops a transient simulation methodology incorporating electrical, thermal, and phase transition models to investigate multibit PCM cell structures and programming strategies. The simulations evaluate two standard PCM structures, namely, the mushroom cell and the confined pillar cell, with feature sizes smaller than 40 nm. The transient simulation captures the phase distribution and cell resistance profile, which are corroborated by transmission electron microscope imaging and the corresponding measured resistance values. This paper also explores a more compact architecture, i.e., the stacked vertical cell, with precise control of Joule heating and potentially more stable intermediate resistance levels. For an electrode area of 10 nm \times 20 nm, a low programming current of \60-\90\ \mu\A generates sufficient heating power to amorphize the phase-change elements sequentially, resulting in four distinct resistance levels distributed over a two-order-of-magnitude resistance range with promise for multibit storage. [ABSTRACT FROM AUTHOR]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

The subthreshold conduction in the amorphous state of the phase-change material is dominated by the hopping of the carriers through the trap states or localized states with the assistance of the electric field across the material. It is important to understand the nature and number of these traps to properly model the physics of the conduction, threshold switching, and drift in phase-change materials. In this paper, we present a device structure and a methodology to extract the trap spacing directly from the I–V characteristics of the device. Furthermore, the dependence of the trap spacing on the amorphous region thickness, reset voltage, and drift is also discussed. These results are then correlated with the \1/f noise measurements of the device. [ABSTRACT FROM AUTHOR]

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (Vth), Vth drift, high resistance state (RESET) resistance (RRESET) drift, and crystallization temperature (Tcrys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. Vth scales down to 0.65–0.5 V (at 25 ^ \circ\C–75 ^\circ\C) for 6-nm-thick \Ge2\Sb2\Te5 (GST), showing that stable read operation is possible in scaled PCM devices. The Vth drift measurement suggests that Vth drift can be attributed to threshold switching field (Eth) drift, whereas Vth0, i.e., Vth at zero thickness, stays almost constant. RRESET drift shows no dependence on the amorphous GST thickness. Tcrys is \sim\!\175 \ ^\circ\C for the device with 6-nm-thick GST, compared with \sim\!\145 \ ^\circ\C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM. [ABSTRACT FROM PUBLISHER]

We study the drift behavior of RESET resistance RRESET and threshold switching voltage Vth in phase-change memory (PCM) and their temperature dependence. To extend the temperature-dependent measurement to microsecond time scales, we integrate an innovative micro-thermal stage (MTS) on the PCM cell. The MTS changes the temperature of the programmed region of the PCM cell within a few microseconds by placing the Pt heater in close proximity of the programmed region. First, we experimentally verify the existing phenomenological RRESET and Vth drift model for constant annealing temperature at various temperatures between 25 ^\circ\C and 185 ^ \circ\C down to 100 \mu\s and show that the measured temperature dependence of the drift coefficient agrees well with what is expected from the existing drift models. Based on the existing drift model for a constant annealing temperature, we derive the analytical expression for the RRESET drift for time-varying annealing temperature and experimentally verify the analytical expression. The derived analytical expression is important to understand the impact of thermal disturbance on PCM reliability such as variations in RRESET and Vth. [ABSTRACT FROM PUBLISHER]

Thermal conduction strongly influences the programming energy and speed in phase-change-memory devices. The thermal conductivity of the crystalline phase of \Ge2\Sb2 \Te5 can be strongly anisotropic due to phase impurities at grain boundaries. This letter models this effect using effective medium arguments, lends further support to the hypothesis that phase impurities are responsible for the anisotropy, and estimates the impact of anisotropic heat conduction on device performance. Electrothermal simulations predict that the reduced in-plane conductivity will allow closer spacing of lateral-cell devices and reduce the reset programming current by 20%–30%. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is a promising candidate for data storage in flexible electronics, but its high switching current and power are often drawbacks. In this study, we demonstrate a switching current density of ~0.1 mega-ampere per square centimeter in flexible superlattice PCM, a value that is one to two orders of magnitude lower than in conventional PCM on flexible or silicon substrates. This reduced switching current density is enabled by heat confinement in the superlattice material, assisted by current confinement in a pore-type device and the thermally insulating flexible substrate. Our devices also show multilevel operation with low resistance drift. The low switching current and good resistance on/off ratio are retained before, during, and after repeated bending and cycling. These results pave the way to low-power memory for flexible electronics and also provide key insights for PCM optimization on conventional silicon substrates. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is an emerging data storage technology; however, its programming is thermal in nature and typically not energy-efficient. Here, we reduce the switching power of PCM through the combined approaches of filamentary contacts and thermal confinement. The filamentary contact is formed through an oxidized TiN layer on the bottom electrode, and thermal confinement is achieved using a monolayer semiconductor interface, three-atom thick MoS2. The former reduces the switching volume of the phase change material and yields a 70% reduction in reset current versus typical 150 nm diameter mushroom cells. The enhanced thermal confinement achieved with the ultra-thin (∼6 Å) MoS2 yields an additional 30% reduction in switching current and power. We also use detailed simulations to show that further tailoring the electrical and thermal interfaces of such PCM cells toward their fundamental limits could lead up to a sixfold benefit in power efficiency. [ABSTRACT FROM AUTHOR]

Phasechange materials are widely considered for application innonvolatile memories because of their ability to achieve phase transformationin the nanosecond time scale. However, the knowledge of fast crystallizationdynamics in these materials is limited because of the lack of fastand accurate temperature control methods. In this work, we have developedan experimental methodology that enables ultrafast characterizationof phase-change dynamics on a more technologically relevant melt-quenchedamorphous phase using practical device structures. We have extractedthe crystallization growth velocity (U) in a functionalcapped phase change memory (PCM) device over 8 orders of magnitude(10–10< U< 10–1m/s) spanning a wide temperature range (415 < T< 580 K). We also observed direct evidence of non-Arrhenius crystallizationbehavior in programmed PCM devices at very high heating rates (>108K/s), which reveals the extreme fragility of Ge2Sb2Te5in its supercooled liquid phase. Furthermore,these crystallization properties were studied as a function of deviceprogramming cycles, and the results show degradation in the cell retentionproperties due to elemental segregation. The above experiments areenabled by the use of an on-chip fast heater and thermometer calledas microthermal stage (MTS) integrated with a vertical phase changememory (PCM) cell. The temperature at the PCM layer can be controlledup to 600 K using MTS and with a thermal time constant of 800 ns,leading to heating rates ∼108K/s that are closeto the typical device operating conditions during PCM programming.The MTS allows us to independently control the electrical and thermalaspects of phase transformation (inseparable in a conventional PCMcell) and extract the temperature dependence of key material propertiesin real PCM devices. [ABSTRACT FROM AUTHOR]

Brain-inspired computing is an emerging field, which aims to extend the capabilities of information technology beyond digital logic. A compact nanoscale device, emulating biological synapses, is needed as the building block for brain-like computational systems. Here, we report a new nanoscale electronic synapse based on technologically mature phase change materials employed in optical data storage and nonvolatile memory applications. We utilize continuous resistance transitions in phase change materials to mimic the analog nature of biological synapses, enabling the implementation of a synaptic learning rule. We demonstrate different forms of spike-timing-dependent plasticity using the same nanoscale synapse with picojoule level energy consumption. [ABSTRACT FROM AUTHOR]

Many chalcogenide glasses undergo a breakdown in electronic resistance above a critical field strength. Known as threshold switching, this mechanism enables field-induced crystallization in emerging phase-change memory. Purely electronic as well as crystal nucleation assisted models have been employed to explain the electronic breakdown. Here, picosecond electric pulses are used to excite amorphous Ag4In3Sb67Te26. Field-dependent reversible changes in conductivity and pulse-driven crystallization are observed. The present results show that threshold switching can take place within the electric pulse on subpicosecond time scales--faster than crystals can nucleate. This supports purely electronic models of threshold switching and reveals potential applications as an ultrafast electronic switch. [ABSTRACT FROM AUTHOR]