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A complete SAW-less transmitter meeting LTE requirements is presented. High power efficiency and low out-of-band noise are obtained exploiting fully current operation of an analog baseband followed by a class-A/B power mixer. Out-of-band emissions are limited by filtering noise and DAC replicas right before the signal up-conversion through a current-mode Biquad feeding directly the power-mixer. The transmitter, implemented in 55 nm CMOS technology, shows -158 dBc/Hz RX-band noise emission at 30 MHz offset for LTE10, while consuming 96 and 34 mW from the single 1.8 V power supply at 4 and -10 dBm output power, respectively. ACLR is always below -42 dBc up to 4 dBm for both LTE10 and LTE20. [ABSTRACT FROM AUTHOR]

An intuitive yet sufficiently accurate formulation of the phase noise of various commonly used oscillators, including most types of class-B (standard, AC-coupled and with tail filter) and class-C, is derived and used to compare their fundamental limitations. A noise factor that represents the difference between the maximum achievable Figure of Merit and the actual one is derived for all topologies considered. Measurements on a dedicated chip prototype that integrates two high performance topologies allow to verify, in an unbiased way, the accuracy of the predictions. A very good agreement between the model and both simulation and measurement is obtained. [ABSTRACT FROM AUTHOR]

A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost constant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switch-pair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal power consumption in the complementary (P-N) configuration is reduced by 75% compared to the single-switch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 nm CMOS 4 GHz DCO prototype show a minimum phase noise of -129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N configuration, and of -134.7 dBc/Hz in the N-only configuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of -185 dBc/Hz. [ABSTRACT FROM AUTHOR]

An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of implementation impairments. The presented prototype shows an in-band phase noise of -108 dBc/Hz, an out-of-band phase noise of -160 dBc/Hz @20 MHz and in-band fractional spurs below -50 dBc. These results are obtained for an output carrier of 1.8 GHz, a reference clock of 26 MHz, with a power consumption of 41.6 mW. [ABSTRACT FROM AUTHOR]

A digitally controlled oscillator (DCO) that achieves a minimum frequency quantization step of 150 Hz without any dithering is presented. The fine digital tuning is obtained through a capacitive degeneration of a portion of the transistor switching pair used in a classical LC-tank oscillator. The new tuning circuitry does not appreciably affect the intrinsic oscillator phase noise and allows to trim the frequency with a programmable resolution for calibration and multi-standard operation. A prototype integrated in 65 nm CMOS technology exhibits a phase noise of -\ 127.5~dBc/\ Hz @ 1 MHz drawing 16 mA from a supply of 1.8 V, resulting in a FoM of 183 dBc/Hz. The active area is 700\ \mu\ m \times \,450\ \mu\ m. [ABSTRACT FROM AUTHOR]