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The resistance of phase-change-memory (PCM) cells measured during RESET programming (dynamic resistance, Rd) is found to be inversely proportional to the amplitude of the programming current, as Rd = [A/I] + B. We show that parameters A and B are related to the intrinsic properties of the memory cell, and demonstrate by means of experimental data that they could be used to characterize the cell-to-cell process-induced variability of PCM cells.

The high current density induced failure in Ge 2 Sb 2 Te 5 (GST)-based phase change memory (PCM) is investigated. A strong dependence of cycling endurance on the polarity of the operation current is observed and reported for the first time. The cycling endurance is reduced by 4 orders of magnitude when the current polarity is reversed. Careful TEM analysis of failed cells revealed a thin void in GST over the bottom electrode, but only in the reverse polarity samples. This phenomenon can be explained by hole-induced electromigration at the electrode/GST interface. The impact of electromigration on scaled phase change memory is discussed.

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

We describe a cycling failure mode in Ge 2 Sb 2 Te 5 -based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10 9 cycles.

Data retention loss from the amorphous (RESET) state over time in Phase-Change Memory cells is associated with spontaneous crystallization. In this paper, the change in the threshold voltage (VT) of memory cells in the RESET state before and after heating is used as a probe into the nature of the retention loss mechanisms. Two mechanisms for the retention loss behavior are identified, responsible for the main distribution and the tail distribution, respectively. Experimental results suggest that (i) an optimized RESET operation produces a fully amorphized Ge2Sb2Te5 (aGST) active region, with no crystalline domains inside, (ii) cells in the tail distribution fail to retain their RESET state due to spontaneous generation of crystallization nuclei and grain growth, and (iii) cells in the main distribution fail due to grain growth from the amorphous/crystalline GST boundary, instead of nucleation within the active region.

A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this dasiadynamic resistancepsila (Rd) is inversely related to the programming current (I), as Rd = [A/I] + B. While the slope parameter A depends only on the intrinsic properties of the phase change material, the intercept B also depends on the effective physical dimensions of the memory element. We demonstrate that these two parameters provide characterization and insight into the degradation mechanisms of memory cells during operation.

We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter is accurately defined by intentionally creating a "keyhole" with conformal deposition. Fully integrated 256 kbit test chips have been fabricated in 180nm CMOS technology. We report SET times of 80 ns, RESET currents less than 250 muA, and accurate sub-lithographic CDs that can be less than 20% the size of the lithographically -defined diameter.

A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900muA at 75nm diameter and multilevel operation are reported