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In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage ($V_{\text {TH}}$) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to −0.82 V, respectively. The degradation of on-state current is also improved significantly from −87% to −40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step $V_{\text {TH}}$ shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C. [ABSTRACT FROM AUTHOR]

The impacts of ammonia gas (NH3) plasma treatment on the performance and positive gate bias stress (PGBS) of polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) are studied. A −0.785-V threshold voltage ($V_{\mathrm {TH}}$) shift of JL-TFT due to the NH3 plasma treatment is observed, which is attributed to the fixed oxide charge effect of the plasma-induced interfacial layer (PIL). In addition, the transconductance of JL-TFT with the NH3 plasma treatment is enhanced by ~2.73 times due to the trap state passivation of grain boundaries in the poly-Si, and the ON-state current ($I_{\mathrm {ON}}$) is enhanced by ~2.91 times. In addition to the performance enhancement of JL-TFT by the plasma process, the $V_{\mathrm {TH}}$ shift of poly-Si JL-TFT under PGBS is suppressed from −0.240 to −0.063 V after the plasma treatment. It is attributed to the less degradation of insulator/channel interface due to the growth of PIL by the plasma process. Moreover, the $I_{\mathrm {ON}}$ degradation of JL-TFT after PGBS is also improved from −19% to −16% after the plasma treatment. As the carrier transport of JL-TFT is the bulk conduction rather than the surface conduction of conventional inversion-mode TFT, the degradation of insulator/channel interface would exhibit less impacts on the $I_{\mathrm {ON}}$. The improvement of performance and PGBS of JL-TFT by the NH3 plasma treatment would be beneficial to the application of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

In this paper, tunnel field-effect transistor (TFETs) with polycrystalline-silicon (poly-Si) channel film has been demonstrated to exhibit better short-channel effects (SCEs) immunity than conventional poly-Si thin-film transistors. Oxygen (O2) plasma surface treatment before the deposition of gate dielectric can produce a plasma-induced interfacial layer, which can passivate the interface trap state density ~25%. In addition, the ON-state transconductance Gm is improved ~54% due to the decrease of tunneling distance of band-to-band tunneling. However, the Gm improvement of poly-Si TFETs is decreased with the scaling down of channel length due to the less trap state density in the small area of poly-Si channel film. Moreover, the O2 plasma surface treatment can also reduce the grain boundary trap state density of poly-Si channel film ~37%, which can reduce the trap-assisted tunneling current of poly-Si TFETs to suppress the length dependence of drain leakage current in the subthreshold region. Consequently, the O2 plasma surface treatment can not only improve the ON-state current and OFF-state leakage current of poly-Si TFETs, but also further improve the SCEs of poly-Si TFETs. [ABSTRACT FROM PUBLISHER]

In this paper, positive-bias temperature instability (PBTI) stress with different stress voltage at T = 125~^\circ \textC is executed on the high-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with HfO2 gate dielectric and ammonia (NH3) plasma surface treatment. The NH3 plasma surface treatment on the poly-Si TFT with HfO2 gate dielectric can significantly decrease the threshold voltage ( V\mathrm{ TH} ) approximately −1.86 V, reduce the subthreshold slope (S.S.) approximately −88 mV/decade, enhance the transconductance ( Gm ) approximately 2.4\times , and driving current ( I_{\mathrm{ drv}}) approximately 2.34. In addition, the device degradation after PBTI stress with stress voltage V_{G} - V_{\mathrm{ TH}} = 7 V for 1000 s at T = 125~^\circ \textC can also be improved after the NH3 plasma surface treatment, such as the suppressing of V\mathrm TH shift from 2.063 to 0.617 V, S.S. degradation quantity from 0.284 V/decade to 0.172 V/decade, and I\mathrm{ drv} reduction from −77% to −44%. The improvement of the PBTI of poly-Si TFTs with NH3 plasma surface treatment is attributed to the suppression of oxide charge trapping effect and the degradation of interface state density ( N\mathrm{ it} ) and grain boundary trap state density ( N\mathrm{ GB} ). [ABSTRACT FROM AUTHOR]

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states ( N\mathrm {{it}} ) near the conduction band edge. The ON-state current ( I\mathrm{\scriptscriptstyle ON} ) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N2 plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N\mathrm {it} obviously, which greatly enhances the surface potential modulation by the gate and improves the I\mathrm{\scriptscriptstyle ON} value of poly-Si TFETs \sim 3.7\times . The OFF-state current ( I_{\mathrm { {min}}} ) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of \sim 40 %, because of the passivation of grain boundary trap ( N\mathrm {trap} ) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42\times 10^{5} to 6.13\times 10^6 . In addition, the subthreshold swing, $I_{{\mathrm{\scriptscriptstyle ON}}}$ , and I_{\mathrm { {min}}} of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device. [ABSTRACT FROM AUTHOR]

In this paper, NH3 plasma directly applied to the surface of poly-Si channel is studied for the development of high-performance low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with HfO2 high- \kappa gate dielectric. The reduction of threshold voltage from 1.52 to 0.62 V, the decrease of subthreshold swing from 227 to 151 mV/decade, and the enhancement of field effect mobility \mu _{\mathrm {FE}} from 31 to 65 cm ^{\mathrm {\mathbf {2}}}$ /Vs are observed after NH3 plasma surface treatment. It can be attributed to the NH3 plasma surface treatment enabling defect passivation and plasma-induced interfacial layer (PIL) growth. To decouple the impacts of defect passivation and PIL growth, the device without PIL is also fabricated. This paper demonstrates the important impacts of NH3 plasma surface treatment on the improvement of electrical characteristics of LTPS-TFTs. [ABSTRACT FROM PUBLISHER]

In this paper, the opposite impacts of N2O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N2O plasma surface treatment is observed, including threshold voltage reduction \Delta V\mathrm {\mathbf {TH}}\sim -0.57 V, 1.55× higher transconductance G\mathit {m} , and 1.82× higher driving current I{\rm{drv}} . However, p-channel LTPS-TFT shows serious performance degradation after N2O plasma surface treatment, including threshold voltage increase \Delta V\mathrm {\mathbf {TH}}~\sim -0.99 V, transconductance G\mathit {m} reduction, and driving current I\mathrm {\mathbf {drv}} degradation. The difference of the two mechanisms of N2O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N2O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit. [ABSTRACT FROM PUBLISHER]