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SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology. [ABSTRACT FROM AUTHOR]

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained. [ABSTRACT FROM AUTHOR]