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High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc. [ABSTRACT FROM AUTHOR]

This paper presents an explicit analysis of the bandwidth and port imbalance of a subquarter-wavelength transmission-line (t-line) transformer and verifies this with the design of a two-stage D-band power amplifier (PA). Series power combining techniques incorporate both stacked heterojunction bipolar transistors (HBTs) and power combining using an 8-way sub-quarter-wavelength t-line transformer above 100 GHz. The extremely compact power combining methodology leads to a small die area of 0.62 mm2 and a record 254-mW/mm2 output power per unit die area. The PA has been fabricated in a 90-nm silicon germanium BiCMOS technology and produces more than 21-dBm output power over the frequency range of 114–130 GHz with a peak output power of $160~{\mathrm{mW}}\approx 22~{\mathrm{ dBm}}$ at 120 GHz and a 3-dB small-signal bandwidth of 35 GHz. This output power is 32% higher than the highest prior art, while the chip area is 77% smaller. [ABSTRACT FROM AUTHOR]

A fully integrated CMOS power amplifier (PA) that efficiently generates high-voltage RF waveforms directly from a 4.8-V supply using only low-voltage thin-oxide transistors is introduced. High-voltage operation is achieved via implicit ~100% efficient dc–dc conversion enabled by stacking and flying individual class-D PA cells in a House-of-Cards (HoC) topology. By dynamically reconfiguring digitally controlled HoC slices to support different voltage conversion ratios and capacitively coupling their outputs, a Doherty-like high-efficiency backoff profile is achieved without using any magnetic impedance inverter. A test chip, implemented in 65-nm low-power CMOS, operates directly from 4.8 V using only 1.2-V transistors, and attains above 40% battery-to-RF efficiency at both 23-dBm peak power and at 6-dB backoff at 720 MHz. When applying a 10-MHz 16-quadrature amplitude modulation signal, the PA achieves an error vector magnitude of 3.6%-rms without using any predistortion techniques with an average output power and power-added efficiency of 15.7 dBm and 26.5%. [ABSTRACT FROM AUTHOR]

An $E$ -band (71–86-GHz) bidirectional transceiver is presented in this paper. The time-division duplex architecture avoids transmit (TX)/receive (RX) switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a wideband PA/LNA circuit, which alleviates the parasitic loading of each circuit through a wideband power combiner. The bidirectional transceiver circuit is implemented in 90-nm SiGe BiCMOS process. In TX mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In RX mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz. The whole RF frontend chip consumes 350.2- and 137.7-mW dc power in TX and RX modes, respectively, including all the RF, IF, and local oscillator amplifiers. The overall chip size is 1.5~\text {mm}\times 0.9 mm including pads. [ABSTRACT FROM AUTHOR]

To increase the voltage handling capability of scaled CMOS-based circuits, series connection (stacking) of transistors has been demonstrated in recently reported mm-wave power amplifiers. This paper discusses the implementation of stacked CMOS circuits employing a compact, multigate layout technique, rather than the conventional series connection of individual transistors. A unit multigate FET is composed of a single transistor with one source and drain and multiple (four) gate connections. Capacitances are implemented in a distributed manner allowing close proximity to the individual gate fingers using metal layers available within the CMOS back-end-of-line (BEOL) stack. The multigate structure is demonstrated to decrease parasitic resistances and capacitances, and has better layout for heat-sinking. The unit cell is replicated through tiling to implement larger effective gate widths. Millimeter-wave power amplifiers using the multigate-cell are presented which operate over the 25–35 GHz band and achieve 300 mW of saturated output power and peak power-added efficiency (PAE) of 30% in 45 nm CMOS SOI technology. To the authors’ knowledge, the output power is the best reported for a single stage CMOS power amplifier that does not use power-combining for this frequency range. [ABSTRACT FROM AUTHOR]

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100-\Omega load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s. [ABSTRACT FROM PUBLISHER]

This paper reports 45-GHz power amplifier (PA) arrays implemented in 45-nm CMOS silicon-on-insulator, coupled to antenna arrays to enable free-space power combining. A single CMOS chip (2.5\,\times\,4.5 \mm^2) containing eight-unit PAs was developed and its output was fed to a 2\,\times\,2 array of differentially fed patch antennas on a printed circuit board. This array provided an equivalent isotropic radiated power (EIRP) of 40 dBm at 45 GHz with 28 dBm of total RF power generated by the chip. A larger array, composed of four CMOS chips and feeding a 2\,\times\,8 array of antennas, was shown to deliver an EIRP of 50 dBm at 45 GHz, while generating a total RF power of 33 dBm together with an antenna array gain of 17 dB. The dc power consumptions for the \2\,\times\,\2 and the 2\,\times\,8 arrays were 4.9 and 18 W, respectively, with estimated peak power-added efficiencies of 13.5% and 10.7%. [ABSTRACT FROM PUBLISHER]

The analysis and implementation of a dual-band direct-conversion millimeter-wave transmitter is presented. The proposed dual-band modulator uses high-impedance loads at two frequencies for the local oscillator driving amplifiers and power amplifier (PA) pre-amplifiers. To correct the amplitude and phase imbalance of the in-phase and quadrature channels at Q- and W-bands, the paper suggests a digitally controlled quadrature error correction stage to finely calibrate these errors and lower the error vector magnitude (EVM) without increasing the baseband digital-to-analog converter resolution. The transmitter is fabricated in 0.12- μm silicon-germanium BiCMOS process and occupies an area of 5.5 mm2. At 45-GHz carrier frequency, error correction improves the sideband suppression ratio (SSR) by 10 dB at 2.4-MHz IF frequency. The EVM is lowered from 3.21% to 2.38% for a 64-QAM constellation at a 2.4-Ms/s symbol rate. At 94-GHz carrier frequency, the SSR is improved from 24 to 41 dBc at 2.4-MHz IF frequency, and the EVM is lowered by more than 1% for a 16-QAM constellation at 3-Ms/s symbol rate. A dual-band PA breakout measurement indicates the peak power-added efficiency of 15% with 14-dBm maximum saturated power (Psat) at 43 GHz and 9-dBm Psat at 82 GHz is achieved. [ABSTRACT FROM AUTHOR]

Gate resistance significantly limits the output power and power-added efficiency of stacked-FET power amplifiers in 45 nm SOI CMOS above 60 GHz. A multi-drive stacked-FET approach is proposed to improve the output power and efficiency. An analysis of conventional and multi-drive stacked-FET PAs demonstrates the performance improvement. A multi-drive three-stack PA is implemented in 45 nm SOI CMOS for 90 GHz operation occupying 0.23 mm 2 . This PA achieves more than 19 dBm output power with peak PAE of 14% and 12 dB gain at 90 GHz using a 3.4 V power supply. [ABSTRACT FROM PUBLISHER]

A 45 GHz active phase-shift Doherty PA is proposed and implemented in 45-nm SOI CMOS. The quarter wave-length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5%, while reducing the die area. Use of slow-wave coplanar waveguides (S-CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two-stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase-shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm^2, and at 6-dB back-off power, the PAE is 21%. [ABSTRACT FROM AUTHOR]

A power amplifier (PA) topology is presented that incorporates a feedback network around the transistor to satisfy matching requirements. Circuit parameters can be tuned for small- and large-signal circuit operation. The PA is fabricated in a 120-nm SiGe BiCMOS process and performs from 36 to 41 GHz. The PA achieves a saturated output power of 23 dBm and a peak power-added efficiency of 20% at 38 GHz. This is the highest reported output power from a single PA at Q-band in silicon. [ABSTRACT FROM PUBLISHER]

The performance of high-efficiency millimeter-wave (mm-wave) power amplifiers (PAs) implemented in a 45-nm silicon-on-insulator (SOI) process is presented. Multistage class-AB designs are investigated for Q- and W-bands and a push–pull amplifier is investigated at Q-band. The Q-band, class-AB PA achieves a saturated output power of 15 dBm and power-added efficiency (PAE) of 27% from a 2-V supply. The W-band, class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% from a 2-V supply. The performance demonstrates the high efficiency possible for mm-wave PAs in a SOI process. [ABSTRACT FROM PUBLISHER]

A fully-integrated Q-band (40–45 GHz) bidirectional transceiver is demonstrated in a 0.12-\mu\m SiGe BiCMOS technology. The RF front-end design eliminates the need for transmit/receive switches by demonstrating a novel PA/LNA circuit. The transceiver has a transmit conversion gain of 35 dB with a 3-\dB bandwidth of 4 GHz. The OP1dB is 8.5 dBm and Psat is 9.5 dBm. The transceiver has a receive conversion gain of 34 dB with a 3-\dB bandwidth of 3 GHz. The noise figure is 4.7 dB and OP1dB is -5 dBm at 43 GHz. The chip consumes 119.4 mW when transmitting and 54 mW when receiving, and overall chip size is 1.6 mm\times 0.8 mm including pads. To the author's knowledge, this work represents the first switchless millimeter-wave bidirectional transceiver in a CMOS or BiCMOS process. [ABSTRACT FROM PUBLISHER]

This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 × 2 oscillator array for a 60-GHz transmitter is fabricated with integrated power amplifiers and on-chip antennas. To lock between multiple dies, an injection-locking scheme appropriate for wire-bond interconnects is described. The 2 × 2 array demonstrates a 200 -MHz locking range and 1 × 4 array formed by two adjacent chips has a 60-MHz locking range. The phase noise of the coupled oscillators is below -100 dBc/Hz at a 1-MHz offset when locked to an external reference. To the best of the authors' knowledge, this is the highest frequency demonstration of coupled oscillators fabricated in a conventional silicon integrated-circuit process. [ABSTRACT FROM AUTHOR]