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Measurement of vibration without having contact with the target is crucial for many applications. However, real time vibration signals are frequently mixed with various levels of dynamic noises. In this research, a non-contact type vibration measurement system based on laser triangulation method is proposed by using a PSD (Position sensitive detector) and here a single axis Brüel and Kjaer piezoelectric accelerometer is used to validate the experimental results. The primary goal of this measurement system is to develop a Gabor Transform based signal denoising technique, in order to eliminate noise from the real-time vibration data. Furthermore, PSD platform vibration, which might cause unanticipated inaccuracies in the detected vibration data, has also been eliminated by utilizing a self-vibration compensation approach using an ADXL-345 three-axis accelerometer. The self-vibration compensated vibration measurement technique has been designed using an NI (national instruments) cRIO (CompactRIO) 9074 real-time FPGA (field programmable gate array) based embedded controller. Consequently, a Gabor Transform and Expansion-based Signal Processing Technique is designed using NI cRIO-9074 real time platform to reduce external noise from the self-vibration compensated vibration data. It has been observed that the implementation of Gabor Transform has improved the performance of the system in term of enhancing the SNR (Signal-to-noise ratio). [ABSTRACT FROM AUTHOR]

In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are unnecessary for the master implementation. We build a one-axis feed drive system that is powered by an AC motor and equipped with an EnDat linear encoder for measuring table speed and position. By performing various experiments for table position and speed control based on the built feed drive system, we verify the performance and practical usefulness of the implemented EnDat interface master. The maximum EnDat clock frequency without the propagation delay compensation is achieved by 2 MHz, which can cope with 16 kHz control cycle frequency. The usefulness is demonstrated by showing the table speed and position control performance that are acceptable in real applications. [ABSTRACT FROM AUTHOR]

The paper proposes the design of a seven-level reduced switch multi-level inverter (7LRS-MLI) topology. The design produces a seven-level staircase output waveform with fewer components (seven power switches), thus reducing the cost and area and improving the performance of the design, i.e. increasing efficiency and reducing switching loss effectively. Both symmetric and asymmetric configurations have been implemented and the results are discussed in the paper. A comparison of the proposed structure with other recent seven-level structures has been illustrated. The simulation (using MATLAB/SIMULINK software) and experimental validation of 7LRS-MLI also have been performed for R, RL load, change in load and change in a modulation index (MI). Field programmable gate arrays (FPGA) have been used for digital implementation of the switching waveforms which reduces design time and improves flexibility. For switching devices, the alternative phase opposite disposition pulse width modulation (APOD-PWM) technique is used at 500 Hz and 5 kHz. The voltage and current total harmonic distortion (THD) profiles are also computed during the simulation and experimental validation. [ABSTRACT FROM AUTHOR]

The frequency synthesizer performs a simple function of generating a desired frequency by manipulating a reference frequency signal, but stable and precise frequency generation is essential for reliable operation in mechanical equipment such as communication, control, surveillance, medical, and commercial fields. Frequency synthesis, which is commonly used in various contexts, has been used in analog and digital methods or hybrid methods. Especially in the field of communication, a precise frequency synthesizer is required for each frequency band, from very low-frequency AF (audio frequency) to high-frequency microwaves. The purpose of this paper is to design and implement a highly reliable frequency synthesizer for application to a railway track circuit systems using AF frequency only with the logic circuit of an FPGA (field programmable gate array) without using a microprocessor. Therefore, the development trend of analog, digital, and hybrid frequency synthesizers is examined, and a method for precise frequency synthesizer generation on the basis of the digital method is suggested. In this paper, the generated frequency generated by applying the digital frequency synthesizer using the ultra-precision algorithm completed by many trials and errors shows the performance of generating the target frequency with an accuracy of more than 99.999% and a resolution of mHz, which is much higher than the resolution of 5 Hz in the previous study. This highly precise AF-class frequency synthesizer contributes greatly to the safe operation and operation of braking and signaling systems when used in transportation equipment such as railways and subways. [ABSTRACT FROM AUTHOR]

Copyright of Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials is the property of MIDEM Society and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The subject of study in this article is the technologies of Field Programmable Gate Array (FPGA), methods, and tools for prototyping of hardware accelerators of Artificial Intelligence (AI) and providing it as a service. The goal is to reduce the efforts of creation and modification of FPGA implementation of Artificial Intelligent projects and provide such solutions as a service. Task: to analyze the possibilities of heterogeneous computing for the implementation of AI projects; analyze advanced FPGA technologies and accelerator cards that allow the organization of a service; analyze the languages, frameworks, and integrated environments for the creation of Artificial Intelligence projects for FPGA implementation; propose a technique for modifiable FPGA project prototyping to ensure a long period of compatibility with integrated environments and target devices; propose a technique for the prototyping of FPGA services with high performance to improve the efficiency of FPGA based AI projects; propose a sequence of optimization of neural networks for FPGA implementation; and provide an example of the practical implementation of the research results. According to the tasks, the following results were obtained. Analysis of the biggest companies and vendors of FPGA technology is performed. Existing heterogeneous technologies and potential non-electronic mediums for AI computations are discussed. FPGA accelerator cards with a large amount of High Bandwidth Memory (HBM) on the same chip package for implementation of AI projects are analyzed and compared. Languages, frameworks, and technologies as well as the capabilities of libraries and integrated environments for prototyping of FPGA projects for the AI applications are analyzed in detail. The sequence of prototyping of FPGA projects that are stable to changes in the environment is proposed. The sequence of prototyping of highly efficient pipelined projects for data processing is proposed. The steps of optimization of neural networks for FPGA implementation of AI applications are provided. An example of practical use of the results of research, including the use of sequences is provided. Conclusions. One of the main contributions of this research is the proposed method of creation of FPGA based implementation of AI projects in the form of services. Proposed sequence of neural network optimization for FPGA allows the reduction of the complexity of the initial program model by more than five times for hardware implementation depending on the required accuracy. The described solutions allow the construction of completely scalable and modifiable FPGA implementations of AI projects to provide it as a service. [ABSTRACT FROM AUTHOR]

This paper proposes a methodology of delivering the emulation hardware of several step-down converter power stages. The generalized emulator design methodology follows these steps: first, the power stage is described using an ordinary differential equation system; second, the ordinary differential equation system is solved using Euler's method, and thus an accurate time-domain model is obtained; next, this time-domain model can be described using either general-purpose programming language (MATLAB, C, etc.) or hardware description language (VHDL, Verilog, etc.). As a result, the emulator has been created; validation of the emulator may be carried out by comparing it to SPICE transient simulations. Finally, the validated emulator can be implemented on the preferred target technology, either in a general-purpose processor or a field programmable gate array. As the emulator relies on the ordinary differential equation system of the power stage, it has better behavioral accuracy than the emulators based on average state space models. Moreover, this paper also presents the design methodology of a manually tuned proportional–integrative–derivative controller deployed on a field programmable gate array. [ABSTRACT FROM AUTHOR]

Encoder interfaces should be operated in real time with high precision and fast processing for industrial motor control systems. The continuous bidirectional serial synchronous (BiSS-C) interface is an open-source serial communication protocol designed for motor encoders and is suitable for industrial purposes because of its fast serial communication speed. In this study, we propose a method for developing a BiSS-C interface master for a motor encoder slave, using only the configurable logic block (CLB) peripheral integrated into TI microcontroller units. By analyzing the detailed operation protocol of the BiSS-C interface, we create the truth and state tables for logic circuits and finite state machines, which are required for the BiSS-C interface master. Then, by programming the CLB based on the created truth and state tables, we implement the master clock, serial peripheral interface (SPI) clock, and operational process for the master. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are not required for the master implementations. The developed method can be immediately applied to developing the masters for other BiSS-C encoders with different specifications, which is certainly necessary for a motor drive development and test. By building an AC motor control system with the developed master and performing various experiments, we verify the performance and practical usefulness of the developed BiSS-C interface master. The maximum master clock frequency without any CRC errors is achieved by 6.25 MHz, which can cope with more than 20 kHz motor control cycle frequency. The usefulness is demonstrated by showing the motor speed and position control performance that are acceptable in real applications. [ABSTRACT FROM AUTHOR]

In this paper, the complex routes to chaos in a memristor-based Shinriki circuit are discussed semi-analytically via the discrete implicit mapping method. The bifurcation trees of period-m (m = 1, 2, 4 and 3, 6) motions with varying system parameters are accurately presented through discrete nodes. The corresponding critical values of bifurcation points are obtained by period-double bifurcation, saddle-node bifurcation, and Neimark bifurcation, which can be determined by the global view of eigenvalues analysis. Unstable periodic orbits are compared with the stable ones obtained by numerical methods that can reveal the process of convergence. The basins of attractors are also employed to analyze the coexistence of asymmetric stable periodic motions. Furthermore, hardware experiments are designed via Field Programmable Gate Array to verify the analysis model. As expected, an evolution of periodic motions is observed in this memristor-based Shinrik's circuit and the experimental results are consistent with that of the calculations through the discrete mapping method. [ABSTRACT FROM AUTHOR]

Compared with off-line digital signal processing (DSP) verification, achieving the expected performance and hardware efficiency in application specific integrated circuit (ASIC) is more critical for DSP to reduce power consumption and cost. The performance of traditional frequency offset compensation algorithms based on feedforward structure is strongly dependent on the accuracy of frequency offset estimation. Therefore, frequency offset calculation and loop filtering implemented in ASIC or field programmable gate array (FPGA) usually choose high word-width fixed-point or floating-point operations, which increase the consumption of logical resources and reduce the clock frequency that hardware logic can achieve. This work proposes a frequency offset compensation scheme based on polar coordinate processing and feedback structure, and a pre-decision-based angle differential estimator is used to estimate the residual frequency offset. In the proposed feedback structure, the frequency offset estimator is realized by a simple accumulator, and the input of the accumulator is the residual frequency offset or its scaling, which will reduce the requirement for the accuracy of the residual frequency offset estimator. The offline verification results show that the performance of the proposed algorithm is close to that of the traditional algorithm, but the proposed algorithm has lower logic resource consumption and higher clock frequency in hardware implementation based on FPGA. The performance of the proposed method is evaluated in real-time through 10-Gbps data rate polarization-multiplexed quadrature phase shift keying modulation after 20-km standard single-mode fiber transmission. Compared with offline processing in MATLAB®, no hardware implementation penalty is observed. [ABSTRACT FROM AUTHOR]

One major functionality of force microscopes is their ability to measure forces at a high sensitivity, thereby, allowing understanding of vital mechanisms: for instance, in bio-specimens. The investigation of a specimen’s viscoelasticity on nano-scale can have significant scientific impact, but has been inhibited by the lack of fast, comprehensive scanning instruments. In principle, transverse dynamic force microscopes (TDFMs) permit the measurement of interaction forces within delicate samples in a noncontact manner. The force measurements are reconstructed via complicated offline analysis in TDFMs, therefore, they can hardly be utilized as an online force measuring tool. This article introduces a novel integrated robust design for practical scanning using the TDFM system. The digital design is implemented in fixed-point arithmetic using field programmable gate array devices, thereby, permitting measurement of the interaction force at a high sampling rate. The novel digital design tackles different implementation issues achieving fast and robust force measuring performance. This enables a new force-scan mode for the TDFM, realizing for the first time, online force mapping of sample-surfaces in real-time. [ABSTRACT FROM AUTHOR]

Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Synchronization, as a unique phenomenon, has been extensively studied in biology, chaotic systems, nonlinear dynamics, quantum information, and other fields. Benefiting from the characteristics of frequency amplification, noise suppression, and stability improvement, synchronization has been gradually applied in sensing, communication, time keeping, and other applications. In the sensing field, synchronization provides a new strategy to improve the performance of sensors. However, the performance improvement is only effective within the synchronization range, and the narrow synchronization range has become a great challenge for the wide application of synchronization-enhanced sensing mechanism. Here, we propose a frequency automatic tracking system (FATS) to widen the synchronization range and track the periodic acceleration signals by adjusting the frequency of the readout oscillator in real time. In addition, a high-precision frequency measurement system and fast response control system based on FPGA (Field Programmable Gate Array) are built, and the tracking performance of the FATS for static and dynamic external signals is analyzed to obtain the optimal control parameters. Experimental results show that the proposed automatic tracking system is capable of static acceleration measurement, the synchronization range can be expanded to 975 Hz, and the relocking time is shortened to 93.4 ms at best. By selecting the optimal PID parameters, we achieve a faster relocking time to meet the requirements of low-frequency vibration measurements, such as seismic detection and tidal monitoring. [ABSTRACT FROM AUTHOR]

In this article, an analysis of an innovative system for filtering signals in the audible range (16 Hz - 20 kHz) on programmable logic devices using a filters with a finite impulse response, is presented. Mentioned system was neat combination of software and hardware platform, where in the program layer a multiple programming languages including VHDL, JavaScript, Matlab or HTML were used to create completely useful application. To determine the coefficients of polynomial filters the Matlab Filter Design & Analysis Tool was used. Thanks to the developed graphic layer, a user-friendly interface was created, which allows easily transfer the required coefficients from the computer to the executive system. The practical implementation made on the FPGA platform, specifically on the Altera DE2-115 development kit with the FPGA Cyclone IV, was compared with simulation realization of Matlab FIR filters. The performed research confirm the effectiveness of filtration in real time with up to 128th order of the filter for both audio channels simultaneously in FPGA-based system. [ABSTRACT FROM AUTHOR]

The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider‐based pseudorandom bit generator is compared with other LCG‐based realisations, showing great improvement. First, a clock divider is utilised for generating a maximum length of 22n pseudorandom bits for n‐bit operands size which leads to lowering the hardware cost. Secondly, it generates high‐speed random bits at a uniform clock rate with one initial clock latency. Third, the proposed technique provides good statistical properties. The proposed architecture is implemented using Verilog HDL and further prototyped on commercially available field programmable gate array (FPGA) devices Virtex‐5, Virtex‐7, and Artix‐7. The realisation of the proposed architecture in these FPGA devices accomplishes an improved data throughput and utilises minimum FPGA resources (in terms of look‐up‐tables and flip‐flops) which are compared with the existing techniques. The generated bit sequence from the experiment is further analysed briefly for sequence size and verified for randomness by using the National Institute of Standards and Technology benchmark test. [ABSTRACT FROM AUTHOR]

Fault detection and diagnosis of a Field‐Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck‐at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair‐wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS'89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis is log2(n(n−1)2)+3 where n is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations by log2(n+2) when compared with previously published methods available in the literature. [ABSTRACT FROM AUTHOR]

Due to its several advantages (especially low volume and weight), power electronic transformer has gained notable attraction in railway applications. The main focus of this work is devoted to development a fully filed programmable gate array (FPGA)‐based control platform for power electronic transformer in the aforementioned application. Due to the parallel processing of FPGAs that results in a faster control algorithm execution, reliable operation (which is of major importance in traction applications) is guaranteed. For this purpose, an input series output parallel power electronic transformer structure is built, and various considerations for reliable and stable operation of the power electronic transformer in traction applications, such as safe start‐up and bidirectional power flow, along with the required control and pulse generation schemes, have been designed and implemented in a Xilinx FPGA control platform. Moreover, a modified control algorithm is proposed for controlling the power electronic transformer in a simple and more reliable manner. This control scheme is developed based on the output voltage of the DC–DC–LLC resonant converter, and can effectively control the sum of rectifier DC‐link voltages and track the input sine reference current, with a lower number of required sensors. Finally, the effectiveness of the proposal has been tested from various aspects by experimental tests. [ABSTRACT FROM AUTHOR]

Recent advances in acquisition equipment are providing experiments with growing amounts of precise, yet affordable sensors. At the same time, an improved computational power, coming from new hardware resources [GPU, field-programmable gate array (FPGA), adaptive compute acceleration platform (ACAP)] has been made available at relatively low costs. This led us to explore the possibility of completely renewing the chain of acquisition for a fusion experiment, where many high-rate sources of data, coming from different diagnostics, can be combined in a wide framework of algorithms. If, on the one hand, adding new data sources with different diagnostics enriches our knowledge about physical aspects, on the other hand, the dimensions of the overall model grow, making relations among variables more and more opaque. A new approach for integrating such heterogeneous diagnostics, based on the composition of deep variational autoencoders, could ease this problem, acting as a structural sparse regularizer. This has been applied to RFX-mod experimental data, integrating the soft X-ray linear images of plasma temperature with the magnetic state. However, to ensure a real-time signal analysis, these algorithmic techniques must be adapted to run in well-suited hardware. In particular, it is shown that, attempting a quantization of neuron transfer functions, such models can be adapted to run in an embedded programmable logic device. The resulting firmware, approximating the deep inference model to a set of simple operations, fits well with the simple logic units that are largely abundant in FPGAs. This is the key factor that permits the use of affordable hardware with complex deep neural topology and operates them in real-time. [ABSTRACT FROM AUTHOR]

A solid state terahertz interferometer has been developed on the recent commissioned HL-2M tokamak. It can work in a wide frequency region of 220–325 GHz, and the terahertz wave is generated from a low frequency phase locked voltage controlled oscillator with the frequency multiplying technique. A phase processor based on field programmable gate array (FPGA) technology is designed for the heterodyne interferometer, and it contributes to real-time display of electron density. To extract phase information, a novel numerical algorithm related to fast Fourier transform is written on the FPGA chip and enables one to obtain phase shift without being affected by amplitude variation induced by plasma absorption or frequency modulation from the outer electromagnetic environment. The interferometer achieves minimum measurable electron density in the order of 1016 m−3. With the plasma diagnosis, electron density and low frequency tearing mode have been measured during the first experimental campaign. [ABSTRACT FROM AUTHOR]

This paper deals with the design and implementation of the conventional Level‐Shifted‐PWM (LS‐PWM) and the PWM‐hybrid modulation techniques in a Field‐Programmable Gate Array (FPGA) development card, applicable to binary asymmetric multilevel converters; particularly herein, the Binary‐Asymmetric Cascade Multilevel Inverter is treated (B‐ACMLI). We employ an FPGA‐based switching‐controller to provide pulses for Multilevel Inverter (MLI) power semiconductors via their gate‐drivers. The modulation strategies were implemented via an FPGA with a 32‐bit floating‐point architecture considering the IEEE‐754 standard's recommendations. The portability of the design is ensured using VHDL. The use of embedded RAM blocks minimizes the logical resources consumed into the FPGA, increases overall speed, and reduces power consumption. A comparison is presented in terms of the number of resources used in both modulation techniques. A low‐cost FPGA board named Pipistrello is used. Pipistrello is an FPGA development board for Xilinx Spartan‐6 LX45, designed by Saanlima Electronics. The platform consisting of a single‐phase seven‐level inverter B‐ACMLI hardware prototype. The experimental results show the effectiveness of the approach. As isolated voltage‐sources, photovoltaic modules are used for the experimental setup to the B‐ACMLI. [ABSTRACT FROM AUTHOR]

The most common impulse noise suppression methods are based on the median filter. They are suitable for low noise densities, but employing a separate noise detection step makes them suitable for higher noise rates. Instead, this may degrade the performance for lower noise. Particularly, the adaptive median noise removal algorithm improves the results for both low and high noise corruption rates. This paper presents a novel noise detection and filtering algorithm that uses leaky integrate and fire spiking neurons which model natural computing of the brain. In the proposed method, at each process of the detection and the filtering, all pixels of an adaptive sliding window are fed to the spiking neurons performing the operations in parallel. As a result, higher processing speed and higher operating frequency are achieved. An FPGA is used to implement the algorithm due to its real-time application and reconfigurable structure. The proposed architecture represents a slight increase in the PSNR values, whereas it consumes less hardware resources compared to the previous works. The design is implemented on Cyclone IV device from Altera family. It includes 3231 LUTs and the maximum operating frequency of 187 MHz is achieved. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Engineering (17264073) is the property of Republic of Iraq Ministry of Higher Education & Scientific Research (MOHESR) and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

High bandwidth, high spatial resolution measurements of electron temperature, density, and plasma potential are valuable for resolving turbulence in the boundary plasma of tokamaks. While conventional Langmuir probes can provide such measurements, either their temporal or spatial resolution is limited: the former by the sweep rate necessary for obtaining I-V characteristics and the latter by the need to use multiple electrodes, as is the case in triple and double probe configurations. The Mirror Langmuir Probe (MLP) bias technique overcomes these limitations by rapidly switching the voltage on a single electrode cycling between three bias states, each dynamically optimized for the local plasma conditions. The MLP system on Alcator C-Mod used analog circuitry to perform this function, measuring Te, VF, and Isat at 1.1 MSPS. Recently, a new prototype digital MLP controller has been implemented on a Red Pitaya Field Programmable Gate Array (FPGA) board which reproduces the functionality of the original controller and performs all data acquisition. There is also the potential to provide the plasma parameters externally for use with feedback control systems. The use of FPGA technology means the system is readily customizable at a fraction of the development time and implementation cost. A second Red Pitaya was used to test the MLP by simulating the current response of a physical probe using C-Mod experimental measurements. This project is available as a git repository to facilitate extensibility (e.g., real-time control outputs and more voltage states) and scalability through collaboration. [ABSTRACT FROM AUTHOR]

Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit. [ABSTRACT FROM AUTHOR]

We present a field-programmable gate array (FPGA) based control system that has been implemented to control a strontium optical lattice clock at the National Physical Laboratory, UK. Bespoke printed circuit boards have been designed and manufactured, including an 8-channel, 16-bit digital to analog converter board with a 2 μs update rate and a 4-channel direct-digital synthesis board clocked at 1 GHz. Each board includes its own FPGA with 28 digital output lines available alongside the specialized analog or radio frequency outputs. The system is scalable to a large number of control lines by stacking the individual boards in a master-slave arrangement. The timing of the digital and analog outputs is based on the FPGA clock and is thus very predictable and exhibits low jitter. A particular advantage of our hardware is its large data buffers that, when combined with a pseudoclock structure, allow complex waveforms to be created. A high reliability of the system has been demonstrated during extended atomic clock frequency comparisons. [ABSTRACT FROM AUTHOR]

The need for efficient Finite Impulse Response (FIR) filters in high-speed applications such as telecommunications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offers many advantages, its convolution nature poises a challenge in parallelization due to data dependency and computational complexity. To resolve this, we propose a novel FPGA-based reconfigurable filter architecture, which processes several data samples in parallel and breaks down data interdependency in a spiral fashion. Experimental results show a throughput of 7.2 GSPS with an operating frequency of only 450 MHz for a filter length of 11 with 16 parallel inputs. With parallelization of 4, it is 4.44 times faster than the state-of-the-art solution for a filter length of 16 and a promising 1.04 GSPS throughput is achieved for a higher order of length 61. Incorporated into a generic Quadrature Amplitude Modulation (QAM) transmitter fitted with Forward Error Correction technique, a maximum throughput of 23 Gb/s is achieved by the system for processing 16 input samples in parallel. In comparison to the state-of-the-art mixed domain approach, a threefold performance gain, while utilizing comparatively less Look-up Tables (LUTs), registers and DSP48 slices with an average gain factor of 43.3 x , 4.7 x and 3.9 x , respectively, is accomplished. [ABSTRACT FROM AUTHOR]

Asymmetric cryptosystems have an important advantage over symmetric systems, since only the public key is transmitted. However, asymmetric cryptographic algorithms have a lower speed compared to symmetric ones. When encrypting and decrypting in asymmetric cryptographic algorithms, complex and cumbersome procedures are used to raise very large numbers to a power modulo (modular exponentiation). In this case, the most resource-consuming operation is the modular reduction operation. One of the solutions to improve performance is the development of high-speed circuit solutions for modular reduction, the main task of which is to obtain the remainder of the division of a reducible number by the module. The structure of a high-speed former of partial remainders based on one binary adder and three comparison circuits is proposed, which can significantly decrease the hardware costs of devices for reducing numbers of multi bits in modulus. Based on the proposed former of partial remainders, a block diagram of a high-speed device for reducing the number modulo with sequential action was developed. Using this principle, a structural block diagram of a device of sequential action of a matrix type is developed. Based on the matrix circuit, a pipelined matrix circuit for reducing the number modulo is designed to process the data stream. A formula is given for estimating the gain in time when processing data streams. Algorithmic validation and verification of the high-speed devices for modular reduction with minimal hardware costs of sequential action was carried out on programmable logic-integrated circuits (FPGAs). For this, The Nexys 4 board based on the Artix-7 Field Programmable Gate Array (FPGA) from Xilinx was chosen. Verilog HDL is used to describe the circuit for reducing a number modulo. The results of a timing simulation of the device are presented in the form of time diagrams for a given 8-bit and 16-bit numbers, confirming the correct operation of the device. [ABSTRACT FROM AUTHOR]

Abstract The Hardware-In-the-Loop (HIL) technique is increasingly used for testing power electronics. FPGAs (Field-Programmable Gate Array) are becoming usual in this kind of emulation due to their acceleration capabilities. But even using FPGAs, it has not been possible to reach real time simulations when small integration steps are necessary (around 100 ns or lower) if floating-point representation is used. Fixed-point has been the solution, but at a high design effort cost. With the release of FPGAs with HFP (Hardened Floating-Point) cores – dedicated floating-point blocks implemented in silicon –, the minimum achievable simulation step decreases significantly. This paper presents a comparison between HFP cores, floating-point in programmable logic and fixed-point for HIL models. Results show that both HFP-based and fixed-point arithmetic achieve a simulation step around 10 ns for a full-bridge converter model. A comparison regarding resolution and accuracy is also presented, because acceleration is not the only issue when decreasing the integration step. Numerical resolution also plays an important role, and 32-bit floating-point representation finds a double barrier: acceleration marked by technology, and numerical resolution. Both are explored in this paper. [ABSTRACT FROM AUTHOR]

Abstract Application Specific Integrated Circuit (ASIC) can facilitate the user with high speed, but a small modification in the algorithm and architecture will lead to more cost in terms of design and development. In contrast Field Programmable Gate Array (FPGA) provides near optimal speed with reconfigurability of algorithm/architecture at any time. From research survey, we come to conclusion that Fast Fourier Transform (FFT) plays critical role in many applications such as Orthogonal Frequency Division Multiplexing (OFDM), image processing application and signal processing application. In this paper, we have developed a reconfigurable FPGA architecture for FFT algorithm. Also, reconfigurable algorithm is proposed to handover the reconfiguration control, so that the datapath can be changed. The proposed reconfigurable FPGA architecture is developed using Verilog and targeted in Altera FPGA boards. The evaluation and comparison of the proposed architecture shows remarkable improvement in terms of throughput, area and power. [ABSTRACT FROM AUTHOR]

This paper presents experimental evaluations of operating speed, power consumption, and chip temperature under various load conditions on commercial FPGAs. To measure the operating speed of FPGAs, we count the oscillation frequency of a ring oscillator (RO), which is implemented on one 4-input look-up table (LUT). The load condition on FPGAs can be controlled by the number of activated ROs in parallel around the measurement RO. The measurement results show that operating speed may be decreased more than10% with 142 ROs as load circuits and the degradation rates depend on the measurement location in an FPGA. The evaluation of die-to-die variations using four more FPGA boards show that there exists a non-negligible speed variation. [ABSTRACT FROM AUTHOR]

The paper presents a parallel series 8-bit converter. The scheme is carried out and implemented in the Xilinx on-board Nexis4DDR. The scheme comprises two 4 bit counters, and a parallel input shift register and a schematic performed in the frequency divider done in VHDL. The sequence of the required clock is obtained by dividing the clock frequency of 100 MHz on-board by means of a division circuit which allows setting the required frequency soft. [ABSTRACT FROM AUTHOR]

For field programmable gate arrays (FPGAs) to retain their semiconductor market and to be competitive as a choice for portable applications, the FPGA industry must adopt new techniques for dynamic and static power reduction. In this paper, a new scheme called ‘self clock-gating’ is introduced to reduce the dynamic power of basic logic elements. Circuits are designed using 16 nm Berkeley’s Predictive technology model and tanner EDA tool is used for simulation. When we consider the average power, proposed architecture consumes 14% lesser than standard architecture. However, proposed architecture consumes only 6% of static power as that of standard architecture. If we consider the energy (power delay product), with the leakage reduction technique, the power delay product is 0.164 femto joules for the proposed architecture but in standard architecture, it is 0.200 femto joules. [ABSTRACT FROM AUTHOR]

In the literature, the parabolic function of the Izhikevich Neuron Model (IzNM) is transformed to the Piecewise Linear (PWL) functions in order to make digital hardware implementations easier. The coefficients in this PWL functions are identified by utilizing the error-prone classical step size method. In this paper, it is aimed to determine the coefficients of the PWL functions in the modified IzNM by using the stochastic optimization methods. In order to obtain more accurate results, Genetic Algorithm and Artificial Bee Colony Algorithm (GA and ABC) are used as alternative estimation methods, and amplitude and phase errors between the original and the modified IzNMs are specified with a newly introduced error minimization algorithm, which is based on the exponential forms of the complex numbers. In accordance with this purpose, GA and ABC algorithms are run 30 times for each of the 20 behaviors of a neuron. The statistical results of these runs are given in the tables in order to compare the performance of three parameter-search methods and especially to see the effectiveness of the newly introduced error minimization algorithm. Additionally, two basic dynamical neuronal behaviors of the original and the modified IzNMs are realized with a digital programmable device, namely FPGA, by using new coefficients identified by GA and ABC algorithms. Thus, the efficiency of the GA and ABC algorithm for determining the nonlinear function parameters of the modified IzNM are also verified experimentally. [ABSTRACT FROM AUTHOR]

Hardware search engines are widely used in network routers for high-speed look up and parallel data processing. Content addressable memory (CAM) is such an engine that performs high-speed search at the expense of large energy dissipation. Match-line (ML) power dissipation is one of the critical concerns in designing low-power CAM architectures. NOR-MLs make this issue more severe due to the higher number of short-circuit discharge paths during search. In this paper, an ML control scheme is presented that enables dynamic evaluation of a match-line by effectively activating or deactivating ML sections to improve the energy efficiency. $128{\boldsymbol \times }32$ -bit memory arrays have been designed using 45-nm CMOS technology and verified at different process-voltage-temperature and frequency variations to test the improvements of performance. A search frequency of 100 MHz under 1-V supply, at 27 °C applied on the proposed CAM results 48.25%, 52.55%, and 54.80% reduction in energy per search compared to a conventional CAM, an early predict and terminate ML precharge CAM (EPTP-CAM) and an ML selective charging scheme CAM, respectively. ML partition also minimizes precharge activities between subsequent searches to reduce total precharge power in the proposed scheme. An approximate reduction of 2.5 times from conventional and EPTP schemes is observed in the precharge dissipation. Besides low search power, proposed design improves the energy-delay by 42% to 88% from compared designs. [ABSTRACT FROM AUTHOR]

The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources. [ABSTRACT FROM AUTHOR]

Time-to-digital convertors (TDCs) based on field programmable gate array (FPGA) are becoming more and more popular. Multi-measurement is an effective method to improve TDC precision beyond the cell delay limitation. However, the implementation of TDC with multi-measurement on FPGAs manufactured with 28 nm and more advanced process is facing new challenges. Benefiting from the ones-counter encoding scheme, which was developed in our previous work, we implement a ring oscillator multi-measurement TDC on a Xilinx Kintex-7 FPGA. Using the two TDC channels to measure time-intervals in the range (0 ns–30 ns), the average RMS precision can be improved to 5.76 ps, meanwhile the logic resource usage remains the same with the one-measurement TDC, and the TDC dead time is only 22 ns. The investigation demonstrates that the multi-measurement methods are still available for current main-stream FPGAs. Furthermore, the new implementation in this paper could make the trade-off among the time precision, resource usage and TDC dead time better than ever before. [ABSTRACT FROM AUTHOR]

A complexity reduction methodology for the ESF-CCS (Engineered Safety Features- Component Control System) based on system analysis is developed in this work. The primary objective of this work is to demonstrate that the adoption of an FPGA (Field Programmable Gate Array) based architecture results in a decrease in the system complexity. The concepts of complexity and complexity metrics, as well as the ways in which the FPGA platform can result in a decrease in complexity, are defined. Following this, an analysis of the ESF-CCS is performed. The sources of complexity are identified and the system complexity is measured using McCabe’s cyclomatic complexity metric. An FPGA-based design with reduced complexity is then presented. The reduction in complexity is achieved by the use of flat hardware logic, System on Chip architecture, and the separation of logically independent functions. By adopting an FPGA architecture, the control logic can be reduced to around a half. This reduction in complexity results in systems with higher reliability, which are easier to test and maintain. [ABSTRACT FROM AUTHOR]

ZYNQ has gradually become a flexible and suitable architecture with field-programmable gate arrays and dual-high-performance advanced RISC machine Cortex-A9 processors in applications of data acquisition and readout systems in the field of nuclear electronics. The high data rate and high-efficient data-throughput performance between the programmable logic (PL) and processing system (PS) is essential in a readout module based on ZYNQ. In this paper, four typical readout electronics system architectures are introduced, and the details of hardware and software design of the new-generation compact readout module RAIN1000Z2 based on ZYNQ XC7Z020–CLG400 are illustrated. Then, the data-throughput performance tests between the PL and PS are designed and implemented. The highest performance readout mode can reach more than 2000 MB/s data-throughput in different high-performance port combination modes. In conclusion, recommendation of combination mode is given for different data-throughput applications’ requirements in readout applications based on the ZYNQ-based readout module. [ABSTRACT FROM PUBLISHER]

Field programmable systems-on-chip (FPS-oCs) are heterogeneous reconfigurable platforms consisting of hard processors and FPGA fabric. They provide software designers with an efficient way to accelerate the execution of their algorithms and hardware designers with much more high-level processing power than that provided by soft-cores implemented in standard logic FPGA resources. Despite these very useful characteristics, the penetration of FPSoCs in digital designs for industrial electronics applications is very limited. There is a general agreement among researchers in the area that one of the main reasons for this is the lack of knowledge about the best way to interconnect the processors and the FPGA fabric in these devices. To address this issue, this paper presents an extensive characterization and analysis of processor-FPGA communications in a widely used family of FPSoCs, namely Cyclone V devices. To the best of authors´ knowledge, this is the most complete study of FPSoCs devices in this regard to date. From the experiments conducted and the results obtained, a set of design guidelines are introduced to help FPSoC designers take the most possible advantage of the excellent characteristics of these devices. [ABSTRACT FROM PUBLISHER]

A fundamental problem in computer vision is finding correspondences between features in pairs of similar images. By comparing feature descriptors instead of pixel intensities, the matching capability is significantly increased. Keypoints extracted by Scale-Invariant Feature Transform (SIFT) provide superior matching ability, however, a small proportion of false corresponcences is always inevitable. The exemption of false matches is achieved using robust fitting algorithms, with RANSAC (random sample consensus) being a popular one. SIFT and RANSAC are computationally demanding and time consuming algorithms. When the target application operates in real-time, conventional approaches based on personal computers usually fail to meet the requirements. In this paper, an FPGA-based architecture for real-time SIFT matching and RANSAC algorithm is presented. The proposed scheme is applied to identify the correspondences between point features across consecutive video frames and reject the false matches. The architecture is verified using the DE2i-150 development board. Using Cyclone IV technology, the system supports a processing rate of 40fps for VGA resolution and therefore meets real-time requirements. [ABSTRACT FROM AUTHOR]

The optimized pure hardware fixed-point implementation of the active disturbance rejection control algorithm on the field programmable gate array (FPGA) is presented in this paper. The optimization of the FPGA resource occupancy is provided with the simulation-based algorithm refinement, the selection of the optimal hardware structure and the modularity principle. In contrast to the conventional very high speed integrated circuit hardware description language (VHDL) approach, the implementation of the proposed optimal hardware design is realized by the system-level design tool, i.e. Xilinx’s System GeneratorTM (XSG). Our methodology demonstrates distinct advantages such as the shorter development time and a simpler optimization procedure of the FPGA resource occupancy. Further, automatically converting the specified XSG model into the VHDL code significantly reduces the coding efforts. The experimental results largely coincide with the simulations and confirm satisfactory system performances in the different working conditions. [ABSTRACT FROM AUTHOR]