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One of the major roadblocks for filamentary type resistive random access memory is variations in both the write voltage and the read resistance. The variation is inevitable because of the stochastic nature of oxygen ion movement inside the metal oxide. In this letter, we show that by inserting a thin SnO2 layer within the HfO2 switching layer, these variations can be significantly reduced. The TiN/HfO2/SnO2/HfO2/Pt material stack achieves ~ 10 times smaller standard deviation for the high resistance state($>100\text{k}\Omega $) cycle to cycle distribution compared with the control group without the SnO2 layer. The tight high resistance state distribution retained after 107 pulse cycling. Incremental RESET pulse measurement indicates that the thin SnO2 acts as an oxygen stopping layer and thus explains the origin of reduced variability. The concept of an oxygen stopping layer is promising for reducing variability for resistive memory. [ABSTRACT FROM AUTHOR]

Increasing computation demand of machine learning (ML) applications (recommender system, image classification, speech recognition, and so on) calls for the development of specialized hardware for ML and neuromorphic computing. New memories, such as resistive random access memory (RRAM), can be used to store weights of neural networks and to accelerate matrix multiplication, the dominant operation in neural networks. One of the key challenges for RRAM-based neural networks is to achieve bidirectional analog conductance modulation for online training. This article provides a programming scheme (SRA: small RESET voltage amplitude and appropriate SET voltage) to achieve bidirectional analog conductance modulation of RRAM devices. We find that both abrupt and gradual SET can be obtained for the same device. The controlling parameters for modulating the gradual SET behavior are the SET voltage and the local device temperature. We suggest that the filament morphology before SET may be the key to understanding this phenomenon; gradual SET is obtained when the filaments have a single-layer gap in the RESET state, and abrupt SET is obtained when the filaments have a multilayer gap in the RESET state. [ABSTRACT FROM AUTHOR]

To increase the density of magnetoresistive random access memory (MRAM) beyond the 1T1MTJ MRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (VTH – VHOLD) when the selector is turned on. Also, exponential-type selectors would degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Ω ⋅ μm2 and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300–500 mV/decade with the current density ~ 1 MA/cm2) and threshold-type selectors (VTH – VHOLD ~250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%–350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RSM) shows potentials for high-capacity storage because of its simple cell structure, small footprint, and good scalability. This two-part article discusses how to implement ultrahigh-density (~terabits) storage with RSM covering design considerations from device to memory array architecture. In Part I of this two-part article, an accurate and computationally efficient model is developed to study 3-D vertical RSM (VRSM). In this article, we use 3-D VRSM with a hexagon-patterned pillar layout (3-D hexagon VRSM) as an example to elaborate our approach. Using the parasitic resistance extracted from physics-based 2-D field solver as the reference, we develop a lumped resistor network for SPICE simulation to accurately capture all leakage currents of the array. This full resistor network is further simplified to a reduced network to achieve high computational efficiency and maintain the full network accuracy (with a relative error <2%). Without this simplification, practical memory array sizes cannot be simulated efficiently. The interplay between the memory cell resistance values and selector nonlinearity (NL) on the maximum array size and the write/read margins under the worst case scenarios is discussed. Large memory cell resistance (low-resistance states ≥100 k) with enough NL (~103) from the selector is recommended for successful write/read operations in a single 3-D hexagonal VRSM array of megabit scale. [ABSTRACT FROM AUTHOR]

A physics-based compact model for retention behaviors of conductive-bridge random access memory (CBRAM) is developed by modeling: 1) the material-dependent metal atom transport from the conductive filament into the electrolyte; and 2) the conduction percolation controlled by the atom concentration. Considering the material properties of the metal and electrolyte, this compact model can well reproduce the retention behaviors of the CBRAM in both low resistance state and high resistance state (HRS) for various material stacks under various operating temperatures. Two types of HRS resistance shift can be reproduced by accurately modeling the percolation paths. The compact model can enable the reliability projection of cells in a crossbar array. [ABSTRACT FROM AUTHOR]

The field of machine learning is witnessing rapid advances along several fronts: new machine learning models, new machine learning algorithms utilizing these models, new hardware architectures for these algorithms, and new technologies for creating energy-efficient implementations of such hardware architectures. Hyperdimensional (HD) computing represents one such model. Emerging nanotechnologies, such as carbon nanotube field-effect transistors (CNFETs), resistive random-access memory (RRAM), and their monolithic 3D integration, enable energy- and area-efficient hardware implementations of HD computing architectures. Such efficient implementations are achieved by exploiting several characteristics of the component nanotechnologies (e.g., energy-efficient logic circuits, dense memory, and incrementers naturally enabled by gradual reset of RRAM cells) and their monolithic 3D integration (enabling tight integration of logic and memory), as well as various characteristics of the HD computing model (e.g., embracing randomness that allows us to utilize rather than avoid inherent variations in RRAM and CNFETs, resilience to errors in the underlying hardware). We experimentally demonstrate and characterize an end-to-end HD computing nanosystem built using monolithic 3D integration of CNFETs and RRAM. Using our nanosystem, we experimentally demonstrate the pairwise classification of 21 languages with measured mean accuracy of up to 98% on >20 000 sentences (6.4 million characters), training using one text sample (~100 000 characters) per language, and resilient operation (98% accuracy) despite 78% of bits in HD representation being stuck at 0 or 1 in hardware. We also show that the monolithic 3D implementations of HD computing can have 35 $\times $ improved energy-execution time product for training and inference of language classification data sets (while using 3 $\times $ less area) compared to silicon CMOS implementations. [ABSTRACT FROM AUTHOR]

Control of cation injection into the switching layer of conductive-bridge random access memory (CBRAM) during switching is a critical factor for CBRAM reliability. Although extrinsic approaches such as the insertion of a transistor in series have proven effective, solutions intrinsic to the CBRAM itself, which are desired for high density cross-point or 3-D vertical memory arrays, are quite limited. In this letter, we show the significant improvement of cycling endurance for Cu-based CBRAM by scaling the switching layer area down to 30 nm in diameter. Further study suggests that the injection of excessive Cu ions into the switching layer is suppressed owing to spatial limitation during the formation of the conductive filament. These results indicate that the area scaling of the switching layer is an effective solution for achieving highly reliable CBRAM devices. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade. [ABSTRACT FROM AUTHOR]

An AC stress test was performed to investigate the accompanying electronic effects in a HfO2 resistive random access memory during the SET transition, which featured a sudden decrease in resistance. Comparing the DC and AC measurement results indicated the pronounced influence of interrupted stress on both the mean values and variations of time to SET. First-principles calculations suggested that the charge states (+2, +1, or neutral) of oxygen vacancies affect the migration barrier for forming oxygen vacancy clusters. Therefore, a charge-state-dependent SET model is proposed to include the additional electronic effects induced by the dynamics of electron trapping and detrapping in oxygen vacancies during AC stress. A trimodal Weibull fitting based on the proposed model reproduced the experimental time to SET distributions obtained in a wide range of AC stress conditions. [ABSTRACT FROM AUTHOR]

The insights contained in Gordon Moore's now famous 1965 and 1975 papers have broadly guided the development of semiconductor electronics for over 50 years. However, the field-effect transistor is approaching some physical limits to further miniaturization, and the associated rising costs and reduced return on investment appear to be slowing the pace of development. Far from signaling an end to progress, this gradual "end of Moore's law" will open a new era in information technology as the focus of research and development shifts from miniaturization of long-established technologies to the coordinated introduction of new devices, new integration technologies, and new architectures for computing. [ABSTRACT FROM PUBLISHER]

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array. [ABSTRACT FROM AUTHOR]

There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both application-specified integrated circuits and field-programmable gate arrays. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1) the area and power costs of our approach can range between 7.4%–165% and 7%–60%, respectively, depending on the design and the attacks targeted; 2) the speed impact can be minimal (close to 0%); 3) our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4) our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse engineering); and 5) our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly. [ABSTRACT FROM AUTHOR]

Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, and new architectures for computation immersed in memory. [ABSTRACT FROM AUTHOR]

The article discusses the potential of the spin-transfertorque magnetic random access memory (STT-MRAM) devices using different physical mechanisms. Details about the STT-MRAM are provided which store information in the magnetization of a nanoscale magnet. Also tackled are the difference in which the design specifications for memory.

In this paper, recent progress of binary metal–oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal–oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed. [ABSTRACT FROM PUBLISHER]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

A physics-based compact device model is developed for the conducting-bridge random-access memory (CBRAM). By considering the dependence of ion migration velocity on the electric field, the vertical and lateral growth/dissolution dynamics for the metallic filament are investigated. Both time-dependent transient and “quasi-static” switching characteristics of the CBRAM are captured. Moreover, the I–V characteristics of the CBRAM can be reproduced. By further considering the compliance effect on the size of the metallic filament, the on-state resistance modulation is fitted, and the multilevel capability is included in the model. This model is verified by the experiments data from the \Ag/Ge0.3\Se0.7-based CBRAM cells. This model reveals that experimentally measured switching parameters such as the threshold voltage and the cell resistance are dynamic quantities that depend on the programming duration time. The time-dependent switching process of the CBRAM is quantified, thus paving the way for a compact SPICE model for circuit simulation. [ABSTRACT FROM PUBLISHER]

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (Vth), Vth drift, high resistance state (RESET) resistance (RRESET) drift, and crystallization temperature (Tcrys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. Vth scales down to 0.65–0.5 V (at 25 ^ \circ\C–75 ^\circ\C) for 6-nm-thick \Ge2\Sb2\Te5 (GST), showing that stable read operation is possible in scaled PCM devices. The Vth drift measurement suggests that Vth drift can be attributed to threshold switching field (Eth) drift, whereas Vth0, i.e., Vth at zero thickness, stays almost constant. RRESET drift shows no dependence on the amorphous GST thickness. Tcrys is \sim\!\175 \ ^\circ\C for the device with 6-nm-thick GST, compared with \sim\!\145 \ ^\circ\C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM. [ABSTRACT FROM PUBLISHER]

A physics-based compact model is developed for III–V field-effect transistors for digital logic applications. Quasi-ballistic ratios, trapezoidal quantum-well subband energy levels, and 2-D source/drain influence on both electrostatics and capacitance are considered. Furthermore, gate tunneling leakage current and parasitic capacitance models are included. These latter effects are important in future technology logic applications, particularly in circuits such as high-density cache arrays. In this paper, we describe the III–V compact model including the gate leakage current and parasitic capacitance analytical models. The efficacy of the compact model in a practical circuit environment is demonstrated using transient simulations of a 6T-static random access memory cell. In addition, we provide design guidelines for optimization of the intrinsic and the extrinsic structure with regard to the parasitic effects. [ABSTRACT FROM AUTHOR]

In this letter, we report ultra-low power (sub-30-nA reset current, I\mathrm {reset}) Ni/HfO2/TiOx/TiN RRAM devices that were fabricated with the rapid thermal oxidation of evaporated titanium. RRAM devices show forming-free, bipolar resistive switching behavior, low-resistive state (LRS) nonlinearity, good data retention, and stability. The resistive switching mechanism is mainly attributed to Schottky barrier modulation induced by \textO^2- migration at the Ni/HfO2 interface. LRS/high-resistive state current conduction is controlled by Schottky emission/trap-controlled space-charge-limited current. The TiOx film is believed to provide a local high-density current for the device, confirmed by conductive atomic force microscope results. [ABSTRACT FROM PUBLISHER]

Devices exhibiting negative differential resistance (NDR), such as resonant tunneling diodes and Esaki-type diodes, offer the promise of converting a dynamic random access memory (DRAM) cell to operate like a static random access memory cell with potentially lower dynamic power dissipation and faster READ and WRITE operations than a conventional DRAM. However, a circuit model that describes the operation of the resulting novel memory cell and is of use for both hand analysis and design, and circuit simulation as has yet been developed due to the non-analytical current-voltage curve of the two NDR devices in the cell. In this paper, we present a "composite" circuit model that describes the relationship between current and voltage at the common node of connection of the two NDR devices. The composite model is analytical and can easily be implemented in SPICE or any circuit simulator. It is also useful for hand analysis of the READ/WRITE performance metrics. Finally, comparisons of composite models are presented. [ABSTRACT FROM AUTHOR]

A SPICE compact model is developed for metal-oxide-based resistive random access memory (RRAM). The model includes the critical impact of temperature change and temporal variation. Using experimental data from \HfOx-based RRAM, the model reproduces both the voltage–time relationship and the cycle-to-cycle variation in the RESET of the memory cells. [ABSTRACT FROM AUTHOR]

The conduction mechanism of metal oxide resistive switching memory is debated in the literature. We measured the I-V characteristics below the switching voltages through TiN/HfOx/Pt memory stack and found the conduction cannot be described by the commonly used Poole-Frenkel model, because the fitted dielectric constant and the trap energy are unreasonable as compared to their known values. Therefore, we provide an alternate viewpoint based on a trap-assisted-tunneling model. Agreement of the bias polarity/temperature/resistance state-dependent conduction behavior was achieved between this model and experimental data. And insights for the multilevel capability due to the control of tunneling distance were obtained. [ABSTRACT FROM AUTHOR]

A physics-based compact model for III–V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak III–V PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-III–V SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM. [ABSTRACT FROM AUTHOR]

The reset mechanism of metal oxide RRAM has been attributed to oxygen ion migration assisted by Joule heating. Here, we present a phenomenological model to provide a unified explanation for both the unipolar and bipolar resistive switching mechanisms. Numerical simulation results reveal that the switching mode is determined by the electrode/oxide interface property. Without/with an interfacial barrier, unipolar/bipolar switching behavior is obtained. This model combines the previous thermal dissolution model and ion migration model and thus can explain many experimental observations such as the electrode-material-dependent switching polarity and the voltage–time dilemma between fast switching and long retention. [ABSTRACT FROM AUTHOR]

\Al2\O3-based RRAM devices were fabricated using atomic layer deposition under 100 ^\circ\C and 300 ^\circ\C deposition temperatures, respectively, and their resistance-switching behaviors were investigated. Both devices show unipolar switching if the top electrode (TE) is made of Ti/Al, whereas the bipolar phenomenon is observed when TE is pure aluminum. Devices fabricated at higher temperature give better uniformity and higher resistance ratio. Ultralow RESET current (\sim\!\!\1\ \mu\A) was obtained, together with adequate voltage margin. [ABSTRACT FROM AUTHOR]

Laserscribing is an attractive reduced graphene oxide (rGO) growthand patterning technology because the process is low-cost, time-efficient,transfer-free, and flexible. Various laser-scribed rGO (LSG) componentssuch as capacitors, gas sensors, and strain sensors have been demonstrated.However, obstacles remain toward practical application of the technologywhere all the components of a system are fabricated using laser scribing.Memory components, if developed, will substantially broaden the applicationspace of low-cost, flexible electronic systems. For the first time,a low-cost approach to fabricate resistive random access memory (ReRAM)using laser-scribed rGO as the bottom electrode is experimentallydemonstrated. The one-step laser scribing technology allows transfer-freerGO synthesis directly on flexible substrates or non-flat substrates.Using this time-efficient laser-scribing technology, the patterningof a memory-array area up to 100 cm2can be completed in25 min. Without requiring the photoresist coating for lithography,the surface of patterned rGO remains as clean as its pristine state.Ag/HfOx/LSG ReRAM using laser-scribingtechnology is fabricated in this work. Comprehensive electrical characteristicsare presented including forming-free behavior, stable switching, reasonablereliability performance and potential for 2-bit storage per memorycell. The results suggest that laser-scribing technology can potentiallyproduce more cost-effective and time-effective rGO-based circuitsand systems for practical applications. [ABSTRACT FROM AUTHOR]

Thermal conduction in GeSbTe films strongly influences the writing energy and time for phase change memory (PCM) technology. This study measures the thermal conductivity of Ge2Sb2Te5 between 25 and 340 °C for layers with thicknesses near 60, 120, and 350 nm. A strong thickness dependence of the thermal conductivity is attributed to a combination of thermal boundary resistance (TBR) and microstructural imperfections. Stoichiometric variations significantly alter the phase transition temperatures but do not strongly impact the thermal conductivity at a given temperature. This work makes progress on extracting the TBR for Ge2Sb2Te5 films, which is a critical unknown parameter for PCM simulations. [ABSTRACT FROM AUTHOR]