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For modeling of complex systems, in signal processing, and the explorations of nonlinear dynamics and memory effects, the utilization of noninteger-order dynamics provides adaptable control over oscillation patterns and frequencies. Moreover, various waveforms result in unique sonic qualities. By manipulation of these waveforms, musicians and sound designers have the capacity to craft a wide spectrum of auditory experiences, ranging from basic tones to intricate sound scape. This paper is about study of such vibrating systems using the noninteger-order derivative operator approach. In particular, we will discuss fractional relaxation oscillator and Scott-Blair oscillator employing constant proportional Caputo fractional derivative operator. Laplace transform method and Tzou’s numerical inversion algorithm are utilized to solve these vibrating models with respective initial conditions. A thorough graphical analysis is done to discuss the control of noninteger-order parameters and the parameters involved in the definition of fractional derivative operator. Finally, useful conclusions are recorded to highlight the behavior of oscillators and influence of noninteger-order parameters, the parameters involved in the definition of fractional derivative operator and system parameters that are helpful in controlling over oscillation pattern, frequencies and shape of vibrations produced by the vibrating systems. [ABSTRACT FROM AUTHOR]

In this paper, we present a CMOS rail-to-rail second-generation voltage conveyor (VCII) suitable for low power applications, implemented in 180 nm CMOS technology with a supply voltage of ± 0.9 V. The proposed VCII consists of a current and voltage buffer operating in class AB. At the input of the voltage buffer, there is a bulk-driven differential amplifier, which provides a rail-to-rail input common-mode voltage. A common source output stage in class AB provides rail-to-rail at the output of the voltage buffer. The transistors are designed to operate in moderate inversion, achieving a relatively large current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively, with a power consumption of 157 μW. A sine wave with an amplitude of 1.5 Vpp and a frequency of 1 MHz on the output buffer has a total harmonic distortion of only 0.29%. The application of VCII in a relaxation oscillator with a frequency of up to 10 MHz is demonstrated, as well as its comparative characteristics with reference to other relevant square-wave generators published in the literature. [ABSTRACT FROM AUTHOR]

A high resolution, acceptable accuracy and low power consumption time-domain temperature sensor is proposed and simulated in this paper based on a 180 nm standard CMOS technology. A diode stacking structure is introduced to enhance the accuracy of the temperature sensing core. To improve the resolution of the sensor, a dual-input capacitor multiplexing voltage-to-time converter (VTC) is implemented. Additionally, a low-temperature drift voltage-mode relaxation oscillator (ROSC) is proposed, effectively reducing the large oscillation frequency drift caused by significant temperature impacts on delay errors. The simulated results show that the resolution is as high as 0.0071 °C over 0∼120 °C with +0.43 °C/−0.38 °C inaccuracy and 1.9 pJ · K2 resolution FoM, consuming only 1.48 μ W at a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a novel compact and shadow resistance‐to‐frequency converter and resistance‐to‐time converter. The design incorporates three current feedback operational amplifiers (CFOA) and can be implemented in CMOS technology. The design's functionality has been proven through simulation and experimental verification. The simulation and experimental findings show that the proposed design works well with small deviation between simulation and experimental results. [ABSTRACT FROM AUTHOR]

The narrowband light from a scannable, single-mode dye laser influences the electrical properties of gas discharges. The variation in these properties as the laser wavelength λ is scanned yields the optogalvanic spectrum of the discharge (i.e., electrical conductivity vs. frequency). By connecting a neon lamp, capacitor, and power supply in parallel, an undriven relaxation oscillator is formed whose natural frequency f0 is affected by neon-resonant laser light and this λ-dependence of the relaxation oscillator frequency f0 yields a variant optogalvanic spectrum (i.e., f0 vs. frequency). In this paper, a driving force is effectively applied to an otherwise undriven oscillator when the incident light is chopped periodically at fd. For fd ≈ f0 and a sufficiently large driving force amplitude (laser intensity and the degree of neon resonance), the relaxation oscillator can be entrained so that f0 is locked on fd and is independent of λ. For the new chopped-light technique described here, fd is adjusted to be the subthreshold of the entrainment range, where the λ-dependence of f0 is advantageously exaggerated by periodic pulling, and the beat frequency |fd − f0| vs. λ provides an optogalvanic spectrum with appealingly amplified signal-to-noise qualities. Beat frequency neon spectra are reported for the cases fd < f0 and fd > f0 and are compared with spectra obtained using the unchopped-light (i.e., undriven) method. [ABSTRACT FROM AUTHOR]

Abstract With remarkable electrical and optical switching properties induced at low power and near room temperature (68 °C), vanadium dioxide (VO2) has sparked rising interest in unconventional computing among the phase-change materials research community. The scalability and the potential to compute beyond the von Neumann model make VO2 especially appealing for implementation in oscillating neural networks for artificial intelligence applications, to solve constraint satisfaction problems, and for pattern recognition. Its integration into large networks of oscillators on a Silicon platform still poses challenges associated with the stabilization in the correct oxidation state and the ability to fabricate a structure with predictable electrical behavior showing very low variability. In this work, the role played by the different annealing parameters applied by three methods (slow thermal annealing, flash annealing, and rapid thermal annealing), following the vanadium oxide atomic layer deposition, on the formation of VO2 grains is studied and an optimal substrate stack configuration that minimizes variability between devices is proposed. Material and electrical characterizations are performed on the different films and a step-by-step recipe to build reproducible VO2-based oscillators is presented, which is argued to be made possible thanks to the introduction of a hafnium oxide (HfO2) layer between the silicon substrate and the vanadium oxide layer. Up to seven nearly identical VO2-based devices are contacted simultaneously to create a network of oscillators, paving the way for large-scale implementation of VO2 oscillating neural networks.

This article presents the design of an integrated, frequency-programmable stimulation circuit dedicated to small rodents for the study of pulmonary arterial hypertension. A complete architecture of the stimulation circuit is proposed, based on in vivo tests that have led to the stimulation waveform specification. The circuit is designed using XFAB 0.18 µm technology. The adopted design methodology allows to reduce the power consumption of command blocks to the minimum. Post-layout simulation results shows that the pacing rate can be tuned from 450 to 600 beats per minute (bpm). The total power consumption of the stimulation circuit is 196.1 µW, with 186 µW directly consumed by the voltage multipliers, H-Bridge and pacemaker load, 10.1 µW by the kilohertz-range VCO driver, and only 8.4 nW by the ultra-low power command generator. [ABSTRACT FROM AUTHOR]

With remarkable electrical and optical switching properties induced at low power and near room temperature (68 °C), vanadium dioxide (VO2) has sparked rising interest in unconventional computing among the phase-change materials research community. The scalability and the potential to compute beyond the von Neumann model make VO2 especially appealing for implementation in oscillating neural networks for artificial intelligence applications, to solve constraint satisfaction problems, and for pattern recognition. Its integration into large networks of oscillators on a Silicon platform still poses challenges associated with the stabilization in the correct oxidation state and the ability to fabricate a structure with predictable electrical behavior showing very low variability. In this work, the role played by the different annealing parameters applied by three methods (slow thermal annealing, flash annealing, and rapid thermal annealing), following the vanadium oxide atomic layer deposition, on the formation of VO2 grains is studied and an optimal substrate stack configuration that minimizes variability between devices is proposed. Material and electrical characterizations are performed on the different films and a step-by-step recipe to build reproducible VO2-based oscillators is presented, which is argued to be made possible thanks to the introduction of a hafnium oxide (HfO2) layer between the silicon substrate and the vanadium oxide layer. Up to seven nearly identical VO2-based devices are contacted simultaneously to create a network of oscillators, paving the way for large-scale implementation of VO2 oscillating neural networks. [ABSTRACT FROM AUTHOR]

Starting from [J.-M. Ginoux et al., Torus breakdown in a uni junction memristor, Int. J. Bifurcation Chaos 28(10) (2018) 1850128; J.-M. Ginoux et al., Torus breakdown in a two-stroke relaxation memristor, Chaos Solitons Fractals 153 (2021) 111594], we define a model which describes the dynamical behavior of a class of two-stroke oscillators (i.e., nonlinear oscillators with two distinct phases per cycle). We highlight some properties of the model still not taken into account, like presence of a global bifurcation and bistability for some regions of the parameters space. We then extend the model to study two coupled two-stroke oscillators, where synchrony and anti-synchrony regimes appear as well as transient chaos and intermittency phenomena. We finally compare the theoretical results on synchrony regimes with the corresponding experimental data obtained from a circuit where two relaxation oscillators, based on the Unijunction Transistor (UJT) electronic component, are coupled together. The comparison shows a good qualitative agreement between the experiments and the theoretical results. [ABSTRACT FROM AUTHOR]

Non-normalizable states are difficult to interpret in the orthodox quantum formalism but often occur as solutions to physical constraints in quantum gravity. We argue that pilot-wave theory gives a straightforward physical interpretation of non-normalizable quantum states, as the theory requires only a normalized density of configurations to generate statistical predictions. In order to better understand such states, we conduct the first study of non-normalizable solutions of the harmonic oscillator from a pilot-wave perspective. We show that, contrary to intuitions from orthodox quantum mechanics, the non-normalizable eigenstates and their superpositions are bound states in the sense that the velocity field v y → 0 at large ± y . We argue that defining a physically meaningful equilibrium density for such states requires a new notion of equilibrium, named pilot-wave equilibrium, which is a generalisation of the notion of quantum equilibrium. We define a new H-function H pw , and prove that a density in pilot-wave equilibrium minimises H pw , is equivariant, and remains in equilibrium with time. We prove an H-theorem for the coarse-grained H pw , under assumptions similar to those for relaxation to quantum equilibrium. We give an explanation of the emergence of quantization in pilot-wave theory in terms of instability of non-normalizable states due to perturbations and environmental interactions. Lastly, we discuss applications in quantum field theory and quantum gravity, and implications for pilot-wave theory and quantum foundations in general. [ABSTRACT FROM AUTHOR]

Dependences of the components of the complex dielectric permittivity and specific electrical conductivity in the frequency range 10−2–107 Hz at temperatures of 213–433 K of guaiacol, a model compound of lignin, one of the most common biopolymers, are analyzed. Three groups of relaxation oscillators are identified. Their characteristics (relaxation time and activation energy) are determined. The activation energy is shown to change depending on the aggregate state. The results indicate that the dielectric relaxation and conductivity of lignin polymer and its model compounds are similar in an alternating electric field. [ABSTRACT FROM AUTHOR]

Sleep timing varies between individuals and can be altered in mental and physical health conditions. Sleep and circadian sleep phenotypes, including circadian rhythm sleep-wake disorders, may be driven by endogenous physiological processes, exogeneous environmental light exposure along with social constraints and behavioural factors. Identifying the relative contributions of these driving factors to different phenotypes is essential for the design of personalised interventions. The timing of the human sleep-wake cycle has been modelled as an interaction of a relaxation oscillator (the sleep homeostat), a stable limit cycle oscillator with a near 24-hour period (the circadian process), man-made light exposure and the natural light-dark cycle generated by the Earth's rotation. However, these models have rarely been used to quantitatively describe sleep at the individual level. Here, we present a new Homeostatic-Circadian-Light model (HCL) which is simpler, more transparent and more computationally efficient than other available models and is designed to run using longitudinal sleep and light exposure data from wearable sensors. We carry out a systematic sensitivity analysis for all model parameters and discuss parameter identifiability. We demonstrate that individual sleep phenotypes in each of 34 older participants (65-83y) can be described by feeding individual participant light exposure patterns into the model and fitting two parameters that capture individual average sleep duration and timing. The fitted parameters describe endogenous drivers of sleep phenotypes. We then quantify exogenous drivers using a novel metric which encodes the circadian phase dependence of the response to light. Combining endogenous and exogeneous drivers better explains individual mean mid-sleep (adjusted R-squared 0.64) than either driver on its own (adjusted R-squared 0.08 and 0.17 respectively). Critically, our model and analysis highlights that different people exhibiting the same sleep phenotype may have different driving factors and opens the door to personalised interventions to regularize sleep-wake timing that are readily implementable with current digital health technology. Author summary: Disrupted sleep has long term health consequences and affects our day-to-day ability to function physically, mentally and emotionally. But what determines when and how long we sleep? It is well-known that daily light exposure patterns determine the timing of the body clock. However, creating mathematical models that can take realistic light exposure patterns and predict plausible sleep timing has been challenging. Furthermore, nearly all previous studies have focused on developing models for average behaviour, yet sleep timing and duration are highly individual. In this paper, we present a simple model that combines sleep regulatory and circadian processes. The model can take individual light exposure patterns and, by fitting physiologically plausible parameters, describe individual mean sleep timing and duration. We test our model on data collected from 34 older participants. Our modelling approach suggests that some of the participants slept late because of physiological factors, while for other individuals, late sleep was a consequence of their light environment. This approach of combining a model with longitudinal data could be implemented in digital health technology such that your smart watch could tell you not only how you slept last night, but also how to change your light environment to sleep better tomorrow. [ABSTRACT FROM AUTHOR]

Oscillatory neural networks (ONNs) exhibit a high potential for energy-efficient computing. In ONNs, neurons are implemented with oscillators and synapses with resistive and/or capacitive coupling between pairs of oscillators. Computing is carried out on the basis of the rich, complex, non-linear synchronization dynamics of a system of coupled oscillators. The exploited synchronization phenomena in ONNs are an example of fully parallel collective computing. A fast system's convergence to stable states, which correspond to the desired processed information, enables an energy-efficient solution if small area and low-power oscillators are used, specifically when they are built on the basis of the hysteresis exhibited by phase-transition materials such as VO2. In recent years, there have been numerous studies on ONNs using VO2. Most of them report simulation results. Although in some cases experimental results are also shown, they do not implement the design techniques that other works on electrical simulations report that allow to improve the behavior of the ONNs. Experimental validation of these approaches is necessary. Therefore, in this study, we describe an ONN realized in a commercial CMOS technology in which the oscillators are built using a circuit that we have developed to emulate the VO2 device. The purpose is to be able to study in-depth the synchronization dynamics of relaxation oscillators similar to those that can be performed with VO2 devices. The fabricated circuit is very flexible. It allows programming the synapses to implement different ONNs, calibrating the frequency of the oscillators, or controlling their initialization. It uses differential oscillators and resistive synapses, equivalent to the use of memristors. In this article, the designed and fabricated circuits are described in detail, and experimental results are shown. Specifically, its satisfactory operation as an associative memory is demonstrated. The experiments carried out allow us to conclude that the ONN must be operated according to the type of computational task to be solved, and guidelines are extracted in this regard. [ABSTRACT FROM AUTHOR]

Fluidic oscillators are no-moving-part actuators that can be used to produce pulsating jets. The characteristics of these devices and of the flow fields they produce are of particular interest in the field of heat transfer, as pulsating impinging jets have been shown to improve heat transfer compared to steady jets. In this study, special focus is given to these characteristics as a preparation for a subsequent thermal study that will evaluate the performance of these pulsed jets against steady jets. The functioning of the device in response to different operating and design parameters is first considered. It was shown that a transition between different operating modes is possible, depending on both the inlet mass flowrate and the width of the feedback channel of the device. This was followed by a study of the velocity fields of the pulsed jets produced by the device. More specifically, attention is given to the developing characteristics and flow structures of the pulsating free jets of air which are then compared to equivalent steady jets. Finally, by taking advantage of the periodic aspect of the flow, the phase-averaged velocity field was reconstructed. Vortex dipoles were detected, tracked and their convection velocity computed from the same data and compared to a theoretical value from the literature. A proper orthogonal decomposition (POD) of the synchronized raw data was then performed to further highlight the presence of these vortex structures and other flow instabilities. [ABSTRACT FROM AUTHOR]

This paper presents a low-power 140 kHz relaxation oscillator (ROSC) for low-frequency clock generators and timers. In voltage-mode ROSCs, unavoidable shunt current consumption results from voltage slewing at the integration capacitor. The proposed circuit employs CMOS thyristor-based decision elements which effectively reduce shunt currents by exploiting internal positive feedback. A complementary-to-absolute temperature (CTAT) current reference compensates for the frequency's temperature sensitivity. In order to achieve high negative temperature coefficient with small area and power overhead, the circuit reuses parts of the positive-to-absolute temperature (PTAT) bias generation block. Moreover, a modified start-up circuit with 3 times faster oscillator power-on is presented. The 0.09 mm 2 oscillator consumes 6.5 nW/kHz at 1.5 V to 2.5 V supply if only the CTAT source is considered, resulting in a power consumption of 907.4 nW at 140 kHz. The measured temperature coefficient of - 514.7 ppm/K in the range of −40 °C to 85 °C shows an improvement of 5.5 times compared to the uncompensated case. A supply sensitivity of 2.62 %/V, a frequency resolution of 2.67 kHz/step, and an average clock jitter of 6.02 ns are achieved. The oscillator is embedded in an ultra-low power system-on-chip for autonomous environmental sensing. [ABSTRACT FROM AUTHOR]

The relaxation oscillator is a type of oscillator that is based on the nature of physical phenomena that tend to return to equilibrium after being distributed. The relaxation–oscillation equation is the primary equation of the process of relaxation–oscillation. In this work, the relaxation–oscillation equation is solved using the residual power series method, which is a fractional order differential equation with defined initial conditions. The results obtained by this method are more reliable and accurate as compared to those obtained by other methods studied previously to solve this equation. The reliability and efficiency of this method are demonstrated by means of three examples with exact solutions compared with approximate solutions by means of errors. The pseudocode of the applied methodology has also been discussed in brief. The residual power series method can be used to solve well-known fractional order differential equations. [ABSTRACT FROM AUTHOR]

This paper proposes a temperature sensor based on temperature-frequency conversion using 180 nm CMOS technology. The temperature sensor consists of a proportional-to-absolute temperature (PTAT) current generating circuit, a relaxation oscillator with oscillation frequency proportional to temperature (OSC-PTAT), a relaxation oscillator with oscillation frequency independent of temperature (OSC-CON), and a divider circuit cascaded with D flip-flops. Using BJT as the temperature sensing module, the sensor has the advantages of high accuracy and high resolution. An oscillator that uses PTAT current to charge and discharge capacitors to achieve oscillation, and utilizes voltage average feedback (VAF) to enhance the frequency stability of the oscillator is tested. Through the dual temperature sensing process with the same structure, the influence of variables such as power supply voltage, device, and process deviation can be reduced to a certain extent. The temperature sensor in this paper was implemented and tested with a temperature measurement range of 0–100 °C, an inaccuracy of +0.65 °C/−0.49 °C after two-point calibration, a resolution of 0.003 °C, a resolution Figure of Merit (FOM) of 6.7 pJ/K2, an area of 0.059 mm2, and a power consumption of 32.9 μW. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS relaxation oscillator with trimming and temperature compensation is presented for the on-chip multi-sensor systems which need MHz level frequency source. The proposed scheme uses a single current branch to charge the capacitor to generate the oscillation with voltage average feedback (VAF) circuit. Binary-weight current trimming array is adopted to reduce the frequency variation caused by the process variation under different process corners. A compensation calibration resistor array with Kelvin connection is utilized to improve the frequency variation with temperature. With the help of VAF, the frequency spread caused by the comparator delay is suppressed. This relaxation oscillator with a typical frequency of 13.4 MHz is implemented in a standard 180 nm CMOS process. Simulation results show that it achieves a frequency temperature coefficient of 28.3 ppm/∘C from − 4 0 ∘ C to 125∘C and a 0.074%/0.1 V frequency variation when supply voltage changes from 2.9 to 3.7 V. [ABSTRACT FROM AUTHOR]

This work demonstrates oscillation frequency modulation in a NbO2-based relaxation oscillator device, in which the oscillation frequency increases with operating temperature and source voltage, and decreases with load resistance. An annealing-induced oxygen diffusion at 373 K was carried out to optimize the stoichiometry of the bulk NbO2 to achieve consistent oscillation frequency shift with device temperature. The device exhibits stable self-sustained oscillation in which the frequency can be modulated between 2 and 33 MHz, and a wider operating voltage range can be obtained. An additional surface treatment step was employed during fabrication to reduce the surface roughness of the bottom electrode and to remove surface contaminants that affect the interfacial properties of the device. The device frequency tunability coupled with high oscillating frequency and high endurance capability of more than 1.5 × 108 cycles indicates that the Pt/NbO2/Pt device is particularly suitable for applications in an oscillatory neural network. [ABSTRACT FROM AUTHOR]

A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator' output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works. [ABSTRACT FROM AUTHOR]

This paper presents a 2.15 µW/MHz at the frequency of 64 MHz relaxation oscillator with a dynamic range of frequency from 47.5 MHz to 80 MHz. To reduce the power consumption and improve energy efficiency, this work employs only one comparator and one capacitor to generate the output clock in comparison with conventional relaxation oscillator structures. A total of 50% ± 5% of the duty cycle is obtained for the output clock by implementing an auxiliary comparator. The proposed relaxation oscillator uses the output voltages of an external low-dropout (LDO) voltage and bandgap reference (BGR) for the required supply and reference voltages, respectively. Two current sources are implemented to provide the required currents for trimming the output frequency and driving the comparators. Measurement results indicate that the relaxation oscillator achieves a temperature coefficient (TC) of 130 ppm/°C over a wide temperature range from −25 °C to 135 °C at the frequency of 64 MHz. The relaxation oscillator consumes 115 µA of current at the frequency of 64 MHz under a low-dropout (LDO) voltage of 1.2 V. The proposed relaxation oscillator is analyzed and fabricated in standard 90 nm complementary metal-oxide semiconductor (CMOS) process, and the die area is 130 µm × 90 µm. [ABSTRACT FROM AUTHOR]

The memelement emulation using Operational Transconductance Amplifiers (OTAs) has been quite popular in the last decade. Interestingly, a detailed literature survey reveals that only voltage-biased OTAs have been used so far, for their emulators, which may be due to the ease of linear memelement function realization (through just bias voltage application by employing a capacitance). But this technique has disadvantages; most commercially available OTAs are current biased, voltage biasing does not provide a better range for tunability, and current biasing is more stable and can be easily provided through current mirrors in large circuits. Therefore, the presented work proposes a Universal memelement emulator (UME) using only current-biased Active elements (which are purely off-the-shelf). The developed UME uses four single output OTAs, one CCII (Second Generation Current Conveyor) along with only three grounded passive elements. Overall, the designed circuit configuration is based on just forty CMOS transistors, which is the least as compared to other existing UMEs. And also, the exhibited operating frequency limit is found to be in the MHz range for memristor and above 100 kHz for other realized memelements. The paper also describes the application examples of proposed UME in the relaxation oscillator and in a neuromorphic circuit exhibiting the Amoeba behavior. To verify the designed circuits, the simulations have been executed in PSPICE using 0.18 µm CMOS technology. Lastly, the realization of the proposed UME has been shown via commercial ICs; LM13700 and AD844, and results are presented. [ABSTRACT FROM AUTHOR]

This paper discusses the application of coupled reactance-less memristor-based oscillators (MBO) with binary output signals in oscillatory networks. A class of binary-coupled memristor oscillators provides simple integration with standard CMOS logic elements. Combining MBOs with binary logic elements ensures the operation of complex information processing algorithms. The analysis of the simplest networks based on MBOs is performed. The typical reactance-less MBO with current and potential inputs is considered. The output responses for input control signals are analyzed. It is shown that the current input signal impacts primarily the rate of memristor resistance variation, while the potential input signal changes the thresholds. The exploit of the potential input for the synchronization of coupled MBOs and current control input in order to provide the necessary encoding of information is suggested. The example of the application of coupled MBOs in oscillatory networks is given, and results of simulation are presented. [ABSTRACT FROM AUTHOR]

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-VPP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm2. The proposed CMCP achieves a CMI robustness of 20 VPP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply. [ABSTRACT FROM AUTHOR]

Electrochemical supercapacitors, one of the storage devices, have attracted much attention owing to their high power density, fast charge-discharge and long cycle life. In this study, we present findings of a hybrid system comprised of gold and polyaniline, fabricated via an in-situ , one pot synthesis route and designed for use in symmetric supercapacitor applications. The gold-polyaniline (Au-PANI) based hybrid material was thoroughly characterized using microscopic, optical, and surface analytical techniques to gain a comprehensive understanding of the system. The electrochemical performance of Au-PANI based electrode was examined using cyclic voltammetry (CV), galvanostatic charge-discharge (GCD) and electrochemical impedance spectroscopy (EIS) techniques. The hybrid system exhibited maximum specific capacitance (C S) 387 F/g at the current density of 12 A/g for three electrode system. The symmetric supercapacitor exhibited a maximum specific capacity (Q S) 303 mAh/g at the current density of 0.1 A/g and achieved a maximum energy density (ED) and power density (PD) of 243 mWh/kg and 619 W/kg at the current density of 0.1 A/g and 0.9 A/g, respectively. Further, the Au-PANI based symmetric device was applied to generate low-frequency waveforms. [Display omitted] • An in-situ , one pot synthesis route is reported for the fabrication of Au-PANI hybrid system. • Au-PANI based hybrid system was applied for supercapacitor application. • The symmetric supercapacitor exhibited specific capacity value of 303 mAh/g at the current density of 0.1 A/g. • The fabricated symmetric device was applied to generate low-frequency waveforms. [ABSTRACT FROM AUTHOR]

A frequency-modulated ultrawideband (FM-UWB) hybrid transceiver, with a high system reuse ratio up to 90%, is fabricated in the 65-nm CMOS process for both short-range wireless communication and high-resolution radar ranging. The radio frequency (RF) front-ends (RFFEs) based on module stacking and current reuse achieve significant RF power savings of about 30% and 50% for the transmitter and the receiver (RX), respectively. The presented IF zero-crossing delay discrimination benefits a high radar resolution less than 1 cm. A multimode relaxation oscillator (OSC) for the reconfigured triangular subcarrier generation and a dual-path ring voltage-controlled oscillator (VCO) for the linear FM, stacked by a wideband push–pull power amplifier (PA), generate an FCC-compliant UWB signal. An active balun embedded low-noise amplifier (LNA) and two symmetric-detuning band-passed filters (BPFs) are stacked with the bandwidth extension to linearly demodulate the UWB FM signal. Experimental results show that the 3.75–4.25-GHz hybrid transceiver has an energy efficiency of 1.9 nJ/bit with an active area of 0.7 mm2 and a power dissipation of 1.9 mW and achieves the RX sensitivity of −71 dBm and the transmitted power of −14.1 dBm, with a bit error rate (BER) of 10−4 at a distance of 4 m under the data rate (DR) of 0.1–1.0 Mbps. The transceiver also achieves the noise figure (NF) of 4.8 dB and the phase noise of −78.6 dBc/Hz at 1-MHz offset frequency. [ABSTRACT FROM AUTHOR]

Availability of a reliable ON-chip oscillator can secure a system-on-chip (SoC) against physical clock attacks by enabling applications such as boot-up using ON-chip oscillator and hardware clock monitors. This article proposes a frequency-error feedback (FEF) loop-based relaxation oscillator for such applications. It suppresses the low-frequency noise and improves the time interval error (TIE) without degrading the period jitter. It also stabilizes the oscillator against supply and temperature variations. A 77-MHz oscillator prototype is fabricated in a commercial 5-nm FinFET process. Operating from 0.9-V digital and 1.2-V analog supplies, the prototype consumes a total of 0.84 mW and occupies an area of 0.0152 mm 2. It achieves a TIE of 3 ns over 10 K cycles which is $3\times $ better than an oscillator without an FEF loop. Chip samples are picked from four wafer split lots. The worst case frequency variation measured from 16 samples is $\pm 0.25\%$ across an analog supply change of 1.1–1.35 V, while a variation of $\pm 0.3\%$ is measured over −40 to $125 ^\circ \text{C}$ temperature from eight samples. [ABSTRACT FROM AUTHOR]

This article presents a bipolar junction transistor (BJT)-based CMOS temperature-to-frequency converter (TFC). A relaxation oscillator (ROSC) consisting of an integrating capacitor, a current source, and a comparator converts the ratio of the complementary-to-absolute-temperature (CTAT) voltage to the proportional-to-absolute-temperature (PTAT) voltage created by the BJT core to frequency. To improve the temperature accuracy, we incorporate a capacitor flipping technique to remove an offset of the comparator and a settling time error when resetting the integrating capacitor. Moreover, bootstrapped NMOS switches with the triple well structure are implemented to suppress leakage current and prevent from forming parasitic BJTs when the negative CTAT is applied to them by the proposed flipping technique. The prototype fabricated in a 0.11- $\mu \text{m}$ CMOS process consumes 3.1- $\mu \text{W}$ power and occupies a 0.025-mm2 active area. Measurements of 18 samples with the digital trimming show an inaccuracy of $\pm 1~^{\circ }\text{C}$ ($3\sigma$) from $- 40\,\,^{\circ }\text{C}$ to $140~^{\circ }\text{C}$. The area- and energy-efficient TFC is applicable to monitor the temperature inside integrated chips. [ABSTRACT FROM AUTHOR]

Vanadium dioxide ( VO 2 ) devices undergo a thermal insulator-metal-transition by current or voltage injection. In this work, we utilize a dedicated Technology Computer-Aided Design (TCAD) modeling approach to simulate thermal-induced resistive switching effects in VO 2 devices. In particular, we investigate how the heat dissipation modulates the VO 2 device behavior. We employ a mixed-mode Simulation Program with Integrated Circuit Emphasis (SPICE)—TCAD approach to simulate the relaxation oscillator circuit based on VO 2 device, and we show the entangled self-oscillatory behavior of temperature and voltage across the device. Our findings provide essential guidelines for the design of VO 2 oscillators to be exploited to realize oscillatory neural networks circuits for neuromorphic computing. [ABSTRACT FROM AUTHOR]

The design of low-phase-noise fully integrated frequency references is often a critical aspect in the development of low-cost integrated circuits for communication interfaces, sensing platforms, and biomedical applications. This work first discusses relaxation oscillator topologies and design approaches aimed at minimizing the phase noise; then, a single-comparator low-phase-noise RC relaxation oscillator is proposed, featuring a novel comparator self-threshold-adjustment technique. The oscillator was designed for a 10 MHz oscillation frequency. Electrical simulations performed on a 0.18 μm CMOS design confirmed that the proposed technique effectively rejects the flicker component of the comparator noise, allowing for a 152 dBc/Hz figure of merit at a 1 kHz offset frequency. The standard deviation of the jitter accumulated across 10k oscillation cycles is lower than 4 ns. The simulated current consumption of the circuit is equal to 50.8 μA with a 1.8 V supply voltage. The temperature sensitivity of the oscillation frequency is also notably low, as its worst-case value across process corners is equal to −20.8 ppm/°C from −55 °C to 125 °C. [ABSTRACT FROM AUTHOR]

A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm2 from a 1-V supply. The 2.25- $\mu \text{A}$ hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40- $\mu \text{W}$ XO features a low-frequency inaccuracy of 4 ppm/V. The 40- $\mu \text{A}$ relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation. [ABSTRACT FROM AUTHOR]

The work endeavors to realize a single Voltage Differencing Current Conveyor (VDCC)-based current-controlled memristor emulator with charge-dependent linear memristance function. Such current-controlled memristors closely model the current (i)–voltage (v) relationship of the popular TiO2-based physical memristor architecture constructed by Hewlett–Packard (HP). The presented emulator circuit comprises only two grounded passive elements and two external MOS transistors along with a VDCC active element and provides the facility of electronic/resistive tunability. It is found through the detailed literature survey that the presented circuit is the most compact design to realize a charge-controlled memristance simulator as compared to any previously reported structure. The designed configuration has been verified through presented simulation results generated using PSPICE based on 0.18 μ m CMOS technology. It has also been validated through relaxation and chaotic oscillators developed using the proposed VDCC-based memristor emulator and output waveforms have been shown. Furthermore, the discussed memristor emulator has been implemented and verified through commercial ICs, AD844 and LM13700. [ABSTRACT FROM AUTHOR]

In the beginning of the Second World War, the French physicist, Yves Rocard, published a book entitled Théorie des Oscillateurs (Theory of Oscillators). In Chapter V, he designed a mathematical model consisting of a set of three nonlinear differential equations and allowing to account for economic cycles. Numerical integration of his model has highlighted a chaotic attractor. Its analysis with classical tools such as bifurcation diagram and Lyapunov Characteristic Exponents has confirmed the chaotic features of its solution. It follows that Rocard's 1941 chaotic econometric model has thus most likely preceded Lorenz' butterfly of twenty-two years. Moreover, apart from this historical discovery which upsets historiography, it is also established that this "new old" three-dimensional autonomous dynamical system is a new jerk system whose solution exhibits a chaotic attractor the topology of which varies, from a double scroll attractor to a Möbius-strip and then to a toroidal attractor, according to the values of a control parameter. [ABSTRACT FROM AUTHOR]

The phenomenon of the metal–insulator phase transition in polycrystalline vanadium dioxide (VO2) films gave rise to a new class of nonlinear dynamical systems that have found application in neuromorphic electronics. In this article, we propose the model of VO2 relaxation oscillator in the fast-slow systems’ approximation with considering thermal processes accompanying the resistivity switching at the metal–insulator transition (MIT). The differential equations describing the oscillator were reduced to dimensionless form. By means of numerical simulations, the nonlinear system was established to exhibit four types of dynamics depending on the applied electric voltage and the small parameter value of the system. The possible phase space trajectories for the dynamical system were considered for all types of dynamics, with the bursting oscillations predicted not having been observed experimentally so far. The results of this work can be applied to the neuromorphic computer operation analysis with VO2-oscillator dynamics that mimics the neural activity. [ABSTRACT FROM AUTHOR]

This paper develops an integrated concept of a relaxation oscillator to increase system frequency stability and to provide anti-noise signals at a nominal frequency of 8.2 MHz using 2 swing-boosting and self-threshold tracking loop methods. In this case, based on the design of a low-power, high-speed CMOS, the proposed relaxation oscillator is provided, which develops high-speed at low power under various operating conditions. To reduce the dependence of the output voltage on the system temperature, considering self-threshold-tracking loop technique, the transient voltage signals from inverter-based comparator devices, the transient voltage signals from inverter-based comparator devices are matched to the corresponding nominal value of the reference voltage, taking into account the self-threshold tracking loop technique. In this way, the proposed self-threshold tracking loop technique compensates for the existing time delay that ensures the required power consumption of the power comparator. The proposed scheme procedure is provided for the design of the methodology considering a 0.18 μm CMOS. Regarding the design processes, an Allan noise variation of 1.56 ppm with − 109 dBc/Hz phase-based noises with an offset frequency of 100 kHz is provided, which develops a jitter period of 7.66 psrms period through the design process. In this case, the corresponding evaluations yield 160.8 dBc/Hz with 5.6 kHz/nW power comparison efficiency, using only 46.3 μW as power consumption. In this respect, the proposed compensation scheme provides a sensitivity of 0.9%/0.1 V, which is very low compared to other conventional loops. According to the proposed relaxation oscillator scheme, there is an internal temperature of 123 ppm/°C, which is evaluated by − 20–100 °C without considering a modification procedure. [ABSTRACT FROM AUTHOR]

Coupled electronic oscillators have recently been explored as a compact, integrated circuit- and room temperature operation-compatible hardware platform to design Ising machines. However, such implementations presently require the injection of an externally generated second-harmonic signal to impose the phase bipartition among the oscillators. In this work, we experimentally demonstrate a new electronic autaptic oscillator (EAO) that uses engineered feedback to eliminate the need for the generation and injection of the external second harmonic signal to minimize the Ising Hamiltonian. Unlike conventional relaxation oscillators that typically decay with a single time constant, the feedback in the EAO is engineered to generate two decay time constants which effectively helps generate the second harmonic signal internally. Using this oscillator design, we show experimentally, that a system of capacitively coupled EAOs exhibits the desired bipartition in the oscillator phases without the need for any external second harmonic injection, and subsequently, demonstrate its application in solving the computationally hard Maximum Cut (MaxCut) problem. Our work not only establishes a new oscillator design aligned to the needs of the oscillator Ising machine but also advances the efforts to creating application specific analog computing platforms. [ABSTRACT FROM AUTHOR]

We investigate the synchronizing properties of two synaptically coupled model neurons in the presence of conduction delays. The neurons are modeled as relaxation oscillators, and they interact through inhibitory synapses that activate rapidly but decay slowly. We derive a reduced system through a slow/fast decomposition process, and special coordinates are introduced into the system. Then we construct a map, for which a stable fixed point corresponds to a stable synchronized periodic (SP) solution. The functional benefit of these coordinates is that, on the stability of an SP solution, the map can be decomposed into one-dimensional submaps. By analyzing these submaps, we examine how conduction delays affect the stability of the SP solution, depending on the period and duty cycle of an intrinsic oscillator and the synaptic decay rate. [ABSTRACT FROM AUTHOR]

Oscillatory Neural Network (ONN) is an emerging neuromorphic architecture with oscillators representing neurons and information encoded in oscillator's phase relations. In an ONN, oscillators are coupled with electrical elements to define the network's weights and achieve massive parallel computation. As the weights preserve the network functionality, mapping weights to coupling elements plays a crucial role in ONN performance. In this work, we investigate relaxation oscillators based on VO2 material, and we propose a methodology to map Hebbian coefficients to ONN coupling resistances, allowing a large-scale ONN design. We develop an analytical framework to map weight coefficients into coupling resistor values to analyze ONN architecture performance. We report on an ONN with 60 fully-connected oscillators that perform pattern recognition as a Hopfield Neural Network. [ABSTRACT FROM AUTHOR]

Neural circuits coordinate with muscles and sensory feedback to generate motor behaviors appropriate to an animal's environment. In C. elegans, the mechanisms by which the motor circuit generates undulations and modulates them based on the environment are largely unclear. We quantitatively analyzed C. elegans locomotion during free movement and during transient optogenetic muscle inhibition. Undulatory movements were highly asymmetrical with respect to the duration of bending and unbending during each cycle. Phase response curves induced by brief optogenetic inhibition of head muscles showed gradual increases and rapid decreases as a function of phase at which the perturbation was applied. A relaxation oscillator model based on proprioceptive thresholds that switch the active muscle moment was developed and is shown to quantitatively agree with data from free movement, phase responses, and previous results for gait adaptation to mechanical loadings. Our results suggest a neuromuscular mechanism underlying C. elegans motor pattern generation within a compact circuit. [ABSTRACT FROM AUTHOR]

An on-chip nanopower RC relaxation oscillator is developed in a 180-nm standard CMOS process, consuming 300 nW while running at 10 kHz. Employing a frequency compensation scheme that reduces the frequency drift introduced by comparator offset and delay, the proposed oscillator achieves a significant low temperature coefficient. Furthermore, a supply regulation structure is used to reduce the frequency sensitivity to supply voltage variations. Post-simulation results show that the frequency variation against temperature is 105 ppm/ ∘ C in the temperature range from 0 to 85 ∘ C, and the line sensitivity is 2.19%/V with the supply voltage changing from 1.05 to 1.45 V. At offset frequencies of 100 Hz and 1 kHz, the simulated phase noises are −50 and −71 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

This paper discusses the application of coupled reactance-less memristor-based oscillators (MBO) with binary output signals in oscillatory networks. A class of binary-coupled memristor oscillators provides simple integration with standard CMOS logic elements. Combining MBOs with binary logic elements ensures the operation of complex information processing algorithms. The analysis of the simplest networks based on MBOs is performed. The typical reactance-less MBO with current and potential inputs is considered. The output responses for input control signals are analyzed. It is shown that the current input signal impacts primarily the rate of memristor resistance variation, while the potential input signal changes the thresholds. The exploit of the potential input for the synchronization of coupled MBOs and current control input in order to provide the necessary encoding of information is suggested. The example of the application of coupled MBOs in oscillatory networks is given, and results of simulation are presented.

This paper proposes a numerical method for solving fractional relaxation-oscillation equations. A relaxation oscillator is a type of oscillator that is based on how a physical system returns to equilibrium after being disrupted. The primary equation of relaxation and oscillation processes is the relaxation-oscillation equation. The fractional derivatives in the relaxation-oscillation equations under consideration are defined in the Φ -Caputo sense. The numerical method relies on a novel type of operational matrix method, namely, the Φ -Haar wavelet operational matrix method. The operational matrix approach has a lower computational complexity. The proposed scheme simplifies the main problem to a set of linear algebraic equations. Numerical examples demonstrate the validity and applicability of the proposed technique. [ABSTRACT FROM AUTHOR]

This article describes a 2.1-MHz relaxation oscillator (RxO) for energy-harvesting Internet-of-Things (IoT) sensor nodes. The RxO features an asymmetric swing-boosted RC network and a dual-path comparator to surmount the challenges of sub-0.5-V operation while achieving temperature resilience. The former enables alternating the common-mode voltages at the output of the RC network to facilitate the sub-0.5-V operation, while the latter is outfitted with a delay generator for tracking the temperature-sensitive delay of the comparator. Prototyped in 28-nm CMOS, the RxO occupies a tiny footprint of 5,200 μm2. The power consumption is 1.4 μW at 0.35 V. The measured temperature stability is 158 ppm/°C (average of seven chips) over −20 °C–120 °C. It scores the best energy efficiency (667 fJ/cycle) among the reported MHz-range RxOs and has a figure-of-merit (181 dB) that compares favorably with the state-of-the-art. [ABSTRACT FROM AUTHOR]

Computing with networks of synchronous oscillators has attracted wide-spread attention as novel materials and device topologies have enabled realization of compact, scalable and low-power coupled oscillatory systems. Of particular interest are compact and low-power relaxation oscillators that have been recently demonstrated using MIT (metal-insulator-transition) devices using properties of correlated oxides. Further the computational capability of pairwise coupled relaxation oscillators has also been shown to outperform traditional Boolean digital logic circuits. This paper presents an analysis of the dynamics and synchronization of a system of two such identical coupled relaxation oscillators implemented with MIT devices. We focus on two implementations of the oscillator: (a) a D-D configuration where complementary MIT devices (D) are connected in series to provide oscillations and (b) a D-R configuration where it is composed of a resistor (R) in series with a voltage-triggered state changing MIT device (D). The MIT device acts like a hysteresis resistor with different resistances in the two different states. The synchronization dynamics of such a system has been analyzed with purely charge based coupling using a resistive (RC) and a capacitive (CC) element in parallel. It is shown that in a D-D configuration symmetric, identical and capacitively coupled relaxation oscillator system synchronizes to an anti-phase locking state, whereas when coupled resistively the system locks in phase. Further, we demonstrate that for certain range of values of RC and CC, a bistable system is possible which can have potential applications in associative computing. In D-R configuration, we demonstrate the existence of rich dynamics including non-monotonic flows and complex phase relationship governed by the ratios of the coupling impedance. Finally, the developed theoretical formulations have been shown to explain experimentally measured waveforms of such pairwise coupled relaxation oscillators. [ABSTRACT FROM AUTHOR]