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This article presents a BJT-based CMOS temperature sensor with a wide sensing range from −50 °C to 180 °C. To effectively relax the sensor resolution requirement and conversion time over the entire temperature range to improve energy efficiency, we introduce a nonlinear subranging readout scheme together with double sampling to achieve dynamic reconfiguration of the sensor readout according to the ambient temperature. We further reduce the sensor power at high temperature by devoting the $\beta $ -cancellation circuit only for BJT biasing while applying a temperature-independent bias current for the other sensor building blocks. Implemented in 0.18- $\mu \text{m}$ CMOS with four-wire connections and switch-leakage compensation based on small BJTs, the proposed sensor chip prototype achieves a high resolution-FoM of 7.2 pJ $\cdot \text{K}^{{2}}$ at 150 °C, while featuring a small sensing error of ±0.45 °C under a 1.5-V supply. [ABSTRACT FROM AUTHOR]

This brief presents a fully integrated low-power, low noise bandgap reference (BGR) with load driving capability. With the BGR core resistors functioning as the feedback network of the current sourcing power transistor, the proposed BGR saves chip area, reduces noise while supporting current load driving. The circuit is implemented in two different processes for performance comparison, namely the $0.18\mathbf {\mathrm {\mu }}\text{m}$ RF CMOS and the BCD mixed-signal CMOS processes. Measurement results from chip samples of the two processes show similar performances, with an average temperature coefficient (TC) of 27.1ppm/°C over $\mathbf {-} 40\mathbf {\mathrm {\sim }} 125\mathbf {^{\circ} }\text{C}$ at a 1.8-V supply. The corresponding measured coefficient of variation ($\mathbf {\mathrm {\sigma }}/\mathbf {\mathrm {\mu }}$) is around 0.3%, and the load driving capability can be up to $800\mathbf {\mathrm {\mu }}\text{A}$. By reusing the feedback resistors, the chip prototype achieved a low noise density of $1.92~\mathbf {\mathrm {\mu }}\text{V}/\surd $ Hz, 285nV/ $\surd $ Hz and 4nV/ $\surd $ Hz at 10 Hz, 10 kHz and 100 kHz, respectively, while consuming a quiescent current of 396nA. The measured power supply rejection (PSR) is −39dB at 5Hz and −45dB at 1MHz. The influence of load current on PSR has also been analyzed and verified. [ABSTRACT FROM AUTHOR]

A bipolar junction transistor (BJT)‐based CMOS temperature sensor exploiting the piecewise BJT process spread compensation property of the base recombination current is proposed to reduce the process variations of the base–emitter voltage (Vbe). The weighted combinations of different on‐chip resistors are explored to minimise their associated process spread. Fabricated in standard 0.18‐μm CMOS, the chip prototype occupies an active area of 0.036 mm2 and draws 3 μA from a 1.2 V supply, with a measured maximum inter‐/intra‐die variation in Vbe of <1.5 mV from −40 to 125°C from two batches. Using the measured Vbe, ΔVbe and the first‐batch‐only calibration parameters, the chip prototype demonstrates an untrimmed batch‐to‐batch inaccuracy of ± 1.5°C (3σ) within the same temperature range (24 samples from 2 batches). [ABSTRACT FROM AUTHOR]

A compact voltage-mode bandgap voltage reference (BGR) is presented. Instead of using overhead circuits, the silicon bandgap narrowing effect is exploited for bipolar junction transistor’s (BJT) curvature reduction and residual curvature correction. Prototype measurements in a 0.18- \mu \textm standard CMOS process show that the curvature of the BJT is effectively reduced from its inherent 3.6 mV to 1.4 mV. The proposed BGR measures a minimum temperature coefficient of 8.7 ppm/ °C from −55 °C to 125 °C by batch trimming one resistor. After a curvature trimming, it further improves to 4.1 ppm/ °C. The BGR has a minimum supply voltage of 1.3 V, 4.3 \mu \textA nominal current consumption, 0.03%/V line sensitivity, and 2 mV/mA load sensitivity at 25 °. The output rms noise in the $0.1\sim 10$ -Hz band measures 10.23 \mu \text{V} . [ABSTRACT FROM PUBLISHER]

This letter presents a compensation topology which minimizes the inter-/intra-die spread and proportional-to-absolute-temperature (PTAT) drift of the base–emitter voltage ( V\text {be} ) of a bipolar junction transistor (BJT). Without using special devices, the base recombination current from a deep-saturated BJT is utilized in this scheme. Before compensation, the V\text {be} standard deviation (STD) of 15 standalone BJTs measures 3.24 mV at 25 °C with constant external bias currents. After compensation, V\text {be} STD of 30 dies from two batches reduces to 1.8 mV with on-chip bias current. The PTAT drift of V\text {be} as that in typical BJT-based designs are also alleviated. [ABSTRACT FROM PUBLISHER]