Search

Radio frequency and broad-band I/O circuit designers may compensate for the capacitance, of electrostatic discharge (ESD) protection elements by designing them into tuned resonators or matched filters, thereby requiring that the protection device capacitance have a high quality factor (Q). In this paper, we explore several ESD protection device options, focusing on improvement in Q. We show that surrounding a grounded-gate nMOS transistor with a deep trench increases its Q, while adding a trigger circuit decreases it. We also show that SiGe diodes are preferred over SiGe n-p--n devices. A detailed analysis of experimental results is provided. [ABSTRACT FROM AUTHOR]

Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise tolerance of SOI domino circuits is thus proposed. The topic of multiple output domino logic in SOI technology is addressed for the first time. Multiple output domino logic is shown to be more prone to bipolar leakage induced upset than regular domino. Many of the design practices used to alleviate bipolar leakage in regular domino are no longer valid due to the multiple output domino logic's inherent design requirements. A novel SOI-specific multiple output domino logic, particularly suitable for adder designs, is introduced to minimize the bipolar leakage risk. [ABSTRACT FROM AUTHOR]

Discusses stress-induced leakage current (SILC) as a result of inelastic rather than elastic trap-assisted tunneling. Thickness dependence at high fields; Use of SILC measurements; Leakage current conduction mechanism; Models of SILC; SILC as a scaling limitation.

Presents an electromigration reliability diagnosis tool (iTEM) for complementary metal oxide semiconductor (CMOS) very-large scale integration (VLSI) circuits. Temperature effect on electromigration reliability; Block diagram of iTEM; Results of electrothermal timing simulation.