Search

The development of guided chemical vapor deposition (CVD) growth of single-walled carbon nanotubes provides a great platform for wafer-scale integration of aligned nanotubes into circuits and functional electronic systems. However, the coexistence of metallic and semiconducting nanotubes is still a major obstacle for the development of carbon-nanotube-based nanoelectronics. To address this problem, we have developed a method to obtain predominantly semiconducting nanotubes from direct CVD growth. By using isopropyl alcohol (IPA) as the carbon feedstock, a semiconducting nanotube purity of above 90% is achieved, which is unambiguously confirmed by both electrical and micro-Raman measurements. Mass spectrometric study was performed to elucidate the underlying chemical mechanism. Furthermore, high performance thin-film transistors with an on/off ratio above 10(4) and mobility up to 116 cm(2)/(V·s) have been achieved using the IPA-synthesized nanotube networks grown on silicon substrate. The method reported in this contribution is easy to operate and the results are highly reproducible. Therefore, such semiconducting predominated single-walled carbon nanotubes could serve as an important building block for future practical and scalable carbon nanotube electronics.

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously. [ABSTRACT FROM AUTHOR]

A full-band analytical model of the equilibrium carrier density for single-wall semiconducting carbon nanotubes (sCNTs) is presented. The carrier density, which is a fundamental property of all semiconductors, is obtained using a semiempirical method for degenerate positions of the Fermi level and shows good agreement with numerical tight-binding results. The quantum capacitance is subsequently derived from the carrier density and used to develop a C-V model with good agreement with experimental quantum capacitance measurements. An analytical model of the gate coupling function of sCNTs is also reported which relates the internal surface potential with the external applied gate voltage. The diameter temperature and Fermi level dependency, and the essential properties of carbon nanotubes device physics are captured in these analytical equations. [ABSTRACT FROM AUTHOR]

The insights contained in Gordon Moore's now famous 1965 and 1975 papers have broadly guided the development of semiconductor electronics for over 50 years. However, the field-effect transistor is approaching some physical limits to further miniaturization, and the associated rising costs and reduced return on investment appear to be slowing the pace of development. Far from signaling an end to progress, this gradual "end of Moore's law" will open a new era in information technology as the focus of research and development shifts from miniaturization of long-established technologies to the coordinated introduction of new devices, new integration technologies, and new architectures for computing. [ABSTRACT FROM PUBLISHER]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are promising candidates for transistors and interconnects for nanoelectronic circuits. Although CNTs intrinsically have excellent electrical conductivity, the large contact resistance at the interface between CNT and metal hinders its practical application. Here, we show that electrical contact to the CNT is substantially improved using a graphitic interfacial layer catalyzed by a Ni layer. The p-type semiconducting CNT with graphitic contact exhibits high on-state conductance at room temperature and a steep subthreshold swing in a back-gate configuration. We also show contact improvement to the semiconducting CNTs with different capping metals. To study the role of the graphitic interfacial layer in the contact stack, the capping metal and Ni catalyst were selectively removed and replaced with new metal pads deposited by evaporation and without further annealing. Good electrical contact to the semiconducting CNTs was still preserved after the new metal replacement, indicating that the contact improvement is attributed to the presence of the graphitic interfacial layer. [ABSTRACT FROM PUBLISHER]

Historically, the off-state current Ioff and the supply voltage Vdd are specified as technology targets for Si metal–oxide–semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III–V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same Ioff and Vdd values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy–delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device I– V and C –V characteristics and treat Ioff and Vdd as “free variables.” Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of Ioff and Vdd and optimal energy–delay for each emerging device. We show that today's best available III–V transistors and CNFETs can outperform the best Si FETs by 1.5–2 and 2–3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III–V-on-insulator, CNFETs, and TFETs are 1.25, 2–3, and 5–10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively. [ABSTRACT FROM PUBLISHER]

A novel contact technique to reduce the effective Schottky barrier height on Ge and III–V high mobility semiconductors is described. Single metals are used in combination with an ultrathin dielectric to tune the metal/semiconductor barrier height toward zero by shifting or suppressing the strong Fermi-level pinning. Barrier height reduction in the metal-insulator-semiconductor (MIS) contact structure is verified through direct measurements and deduced from increased diode current and reduced contact resistance. Current demonstrations of the MIS contact have barriers as low as 0.05 eV for Er/SiN/n-Ge and 0.18 eV for Al/Al2O3/n-GaAs. The underlying physics is discussed along with the dependence of the minimum achievable contact resistance and barrier height on the metal, dielectric material, dielectric thickness, and substrate doping. For Ge, the MIS contact provides a possible solution to the low n-type Ge dopant solubility problem and allows for the fabrication of Schottky barrier field-effect transistors. For III–V semiconductors, the MIS contact allows for the use of a non-alloyed contact that is crucial for the scalability of III–V metal oxide semiconductor field-effect transistors. [ABSTRACT FROM AUTHOR]

We present analyses for ACCNT (pronounced as “accent”), which is a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high ON–OFF ratios while preserving current drive. We analyze the ACCNT methodology in terms of its tradeoffs and explore optimizations that may serve as future design guidelines. We also investigate circuit-level considerations and the impact of density variation on the ACCNT design. We find that ACCNT can improve the yield of a one-million transistor chip from 0% (conventional CNT design) up to 99% at a cost of \3.3\times area overhead if the fraction of semiconducting CNTs is improved to 99.9%. [ABSTRACT FROM PUBLISHER]

Carbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. The following two fundamental challenges prevent the fabrication of CNFET circuits with the aforementioned advantages: 1) misaligned and mispositioned CNTs and 2) metallic CNTs. Misaligned and mispositioned CNTs can cause incorrect functionality. This paper presents a technique for designing arbitrary logic functions using CNFET circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mispositioned CNTs. Experimental demonstration of misaligned and mispositioned CNT-immune logic structures is also presented. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large- (digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET- device model incorporating the additional device/circuit-level nonidealities and multiple CNTs reported in the paper of Deng and Wong. [ABSTRACT FROM AUTHOR]

In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input NAND gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications. [ABSTRACT FROM AUTHOR]

Devices exhibiting negative differential resistance (NDR), such as resonant tunneling diodes and Esaki-type diodes, offer the promise of converting a dynamic random access memory (DRAM) cell to operate like a static random access memory cell with potentially lower dynamic power dissipation and faster READ and WRITE operations than a conventional DRAM. However, a circuit model that describes the operation of the resulting novel memory cell and is of use for both hand analysis and design, and circuit simulation as has yet been developed due to the non-analytical current-voltage curve of the two NDR devices in the cell. In this paper, we present a "composite" circuit model that describes the relationship between current and voltage at the common node of connection of the two NDR devices. The composite model is analytical and can easily be implemented in SPICE or any circuit simulator. It is also useful for hand analysis of the READ/WRITE performance metrics. Finally, comparisons of composite models are presented. [ABSTRACT FROM AUTHOR]

The theoretical performance of carbon nanotube field-effect transistors (CNFETs) with Schottky barriers (SBs) is examined by means of a general ballistic model. A novel approach is used to treat the SBs at the metal-nanotube contacts as mesoscopic scatterers by modifying the distribution functions for carriers in the channel. Noticeable current reduction is observed compared to previous ballistic models without SBs. Evanescent- mode analysis is used to derive a scale length and the potential profile near the contacts for radially symmetric CNFET structures. Band-to-band tunneling current and ambipolar conduction are also treated. The effects of different device geometries and different nanotube chiralities on the drain-current are studied using this simple model. Quantum conductance degradation due to SBs is also observed. [ABSTRACT FROM AUTHOR]

This paper proposes a simple and accurate expression for inverter effective drive current for nanoscale Si and carbon nanotube FET (CNFET) performance benchmarking. The choice of Ieff = (INL + INM + INH - IP)/3, where INL = IDS(N-FET) (VGS = 0.5VDD, VDS = VDD), INM = IDS(N-FET) (VGS = 0.75VDD, VDS = 0.75VDD), INH = IDS(N-FET) (VGS = VDD, VDS = 0.5VDD), and IP = ISD(P-FET) (VSG = 0.25VDD, VSD = 0.25VDD), includes the effects of both the nFET and the pFET of an inverter and accurately captures the inverter delay performance over many CMOS technology nodes and in the presence of device nonidealities. The proposed metric indicates that the performance enhancement of CNFETs over Si MOSFETs is not as large as that predicted by IDSsat in a circuit environment because of the nonideal I-V characteristics. [ABSTRACT FROM AUTHOR]

Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors, NiSi-gate workfuncfion control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi2. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance. [ABSTRACT FROM AUTHOR]

We show that the conventional nonparabolic approximation of real band structures can be modified and generalized to approximate the complex band structures of common semiconductors with a significant improvement of accuracy against the parabolic approximation. The improvement is due to the inherent elliptic nature of the complex band structures in the vicinity of the bandgap, which has a critical impact on the band-to-band tunneling probability. Important parameters are extracted and tabulated for Si, Ge, GaAs, and GaSb, with a maximum error of < 1.4% compared to the numerical target. [ABSTRACT FROM PUBLISHER]

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106. Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state. [ABSTRACT FROM AUTHOR]