Search

Abstract: We measured the delay times of several components of the rapid single-flux-quantum (RSFQ) circuit using ring oscillators so as to improve the precision in the timing design. The delay time deviates from the designed value because of wafer-to-wafer and on-wafer parameter spreads. In addition, three-dimensional structures of the actual circuits generate unpredictable parasitic inductances, which occasionally lead to the large timing deviation from the design. The 1-σ local spread of the delay time originating from the fabrication was found to be 5.2% for a Josephson transmission line (JTL) composed of two junctions. This result provides a quantitative indication of timing margins required between SFQ pluses. However, the delay times tended to be smaller than those in numerical simulation by approximately 20%. We think that this is because the timing parameters were extracted without any considerations of the parasitic inductance of shunt resistors in the simulation. To examine the influence of the parasitic inductance, we designed four JTLs having additional inductances in series with shunt resistors, and measured each delay time. The decreasing ratio of delay time to the parasitic inductance was found to be 0.32ps per 1 pH. We estimated that the parasitic inductance connected in series with a shunt resistor was 1.6 pH for the JTL. This timing consideration is applicable to all the cells because the junctions used in the actual circuits have roughly the same geometry as that of the JTL. [Copyright &y& Elsevier]

Abstract: We propose an integer multiplier with systolic array structure for single-flux-quantum (SFQ) technology. Since SFQ logic circuits work by pulse logic, suitable circuit structure for SFQ logic circuits is different from one for semiconductor logic circuits. The systolic array is a circuit structure for VLSIs and consists of regularly arranged simple processing elements. All signals of the proposed systolic multiplier flow from input to output unidirectionally. This feature matches concurrent-flow clocking well. For evaluating the proposed systolic multiplier, we have designed a 4-bit systolic multiplier, as well as a 4-bit array multiplier which is one of the most typical parallel multipliers, and have compared them with each other. From the results of the design and the digital simulation, the number of Josephson junctions (JJs) of the 4-bit systolic multiplier is almost the half of that of the 4-bit array multiplier, and the latency of the former is about 1.5 times longer than that of the latter. Our estimation of the performance of larger-scale multipliers shows that the proposed systolic multiplier achieves comparable latency to the array multiplier, using extremely smaller number of JJs when the bit-width of input becomes large. We have fabricated a 1-bit cell of the systolic multiplier using NEC standard Nb process and have successfully tested it at low speed. The proposed systolic integer multiplier is attractive for SFQ technology. [Copyright &y& Elsevier]

Abstract: We have demonstrated the components of datapath toward single-flux-quantum microprocessors based on our new architecture called the forwarding architecture. In the forwarding architecture, we improve the performance by utilizing multiple ALUs to conceal the inefficiency of bit-serial processing. The key components of the datapath are a register file and cascaded ALUs. We have designed the register file to hold four bit-serial data with two read ports and one write port. In each ALU, we have implemented six functionalities: addition, subtraction, logical AND, OR and Exclusive OR operations, and comparison with zero. We have tested the register file and the ALU using high-speed on-chip testing, and confirmed the correct operations up to 18GHz and 23GHz, respectively. [Copyright &y& Elsevier]

Abstract: We have calculated a bit-error-rate (BER) of Josephson latching drivers using the Monte-Carlo simulations taking into account the thermal noise at the Josephson junctions. The latching driver under investigation is composed of parallel 8-junction stacks and a SQUID input gate. We have optimized the structure of the SQUID input gate based on the BER simulation to get larger bias margins with acceptable BER. We have shown that the bias margins of the latching driver with a 3-junction SQUID input gate are better than that using a 2-junction SQUID input gate. The high-speed measurement of the Josephson latching driver confirms the validity of the BER based optimization. We have obtained the BER lower than 10−12 at 5GHz and 10−5 at 10GHz in the Josephson latching driver with the 3-junction SQUID input gate by the high-speed test. [Copyright &y& Elsevier]

We demonstrated the 4 × 4-cross/bar-40 Gbps/ch switch which is functionally compatible with a commercial semiconductor one in order to evaluate the current SFQ circuit technology quantitatively in both a operating speed and power consumption. According to our numerical simulations, the SFQ switch has one or two orders of magnitude higher throughput per a single channel than that of the semiconductor, and has much smaller exchanging times between routing paths. In an actual test based on the NEC Nb-2.5 kA/cm² junction technology, correct operation using an on-chip test system made up of 4700 Josephson junctions was confirmed up to 37 Gbps/ch which is about 14 times faster than the semiconductor of 2.7 Gbps/ch speed. We also confirmed that SFQ circuits consumed 1/800 power compared with those of semiconductor. The reason why data rates obtained experimentally did not reach the designed speed of 40 Gbps/ch is due to both the liming error and the influence of magnetic fields caused by large bias currents exceeding 500 mA. These results of quantitative evaluation show that the SFQ technology has much greater potentials than the semiconductor one in both the operating speed and the power consumption, which means it is very effective to apply the SFQ technology to digital applications. [ABSTRACT FROM AUTHOR]

We have been developing an SFQ shift register memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift register memory is composed of shift registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the memory system at high speed. The tested circuit is a 4-byte shift register file, where four kinds of wiring circuits are used between a decoder and shift registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the memory system. We have used the NEC 2.5 kA/cm2 Nb standard process and the CONNECT cell library. [Copyright &y& Elsevier]

We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the variable number of SFQ pulses according to its internal state. The PCG is composed of an SFQ ring oscillator, a control circuit which counts up the number of SFQ pulses and stops the operation of the ring oscillator, and a decoder which defines the initial state of the control circuit. The PCG can generate the variable number of SFQ pulses ranging from 2 to 2N, where N is the number of T flip-flops in the control circuit. The oscillation frequency of the PCG is designed to be ranging from 6.2 to 18.8 GHz. In this study, we have implemented a PCG generating SFQ pulses ranging from 2 to 24 using a cell-based design methodology and confirmed its correct functionality. [Copyright &y& Elsevier]

We have developed essential components for most of microarchitectures based on the single-flux-quantum (SFQ) logic. The circuit under test is composed of two registers, an ALU and a control unit, and made up of about 540 cells, 1600 Josephson junctions on 1.5 × 2.4 mm area. We have obtained the correct results by a sequence of several instructions, in which two integers are written into the registers with the LOAD and COPY operations, and then execute the ADD operation. Some of their functions were tested at both low and high frequencies. As a result, we found that the designed components could work at 15 GHz for the designed bias current and up to 18 GHz for higher bias currents. [Copyright &y& Elsevier]