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Si dangling bond interface defects (P[sub b0],P[sub b1]) were probed by electron spin resonance in entities of (100)Si with ultrathin SiO[sub 2] grown in ozonated de-ionized water solution at room temperature. After photodesorption of passivating hydrogen, P[sub b0] appears with densities up to ∼ 5 × 10[sup 12] cm[sup -2], a value five times larger than the one standardly attained with high temperature thermal growth. Thus standard quality thermal Si/SiO[sub 2] interface properties, as exposed by the P[sub b0]-type defects criterion (interface traps), are not obtained by oxidation in ozonated water solutions at room temperature. The interface quality may be upgraded by providing additional thermal budget. Yet standard qualitity is still not attained after vacuum annealing at 600°C. [ABSTRACT FROM AUTHOR]

Plasma-assisted atomic layer deposition (ALD) was used to deposit SiO2 films in the temperature range of Tdep = 50-400°C on Si(100). H2Si[N(C2H5)2]2 and an O2 plasma were used as Si precursor and oxidant, respectively. The ALD growth process and material properties were characterized in detail. Ultrashort precursor doses (∼50 ms) were found to be sufficient to reach self-limiting ALD growth with a growth-per-cycle of ∼1.2 Å (Tdep = ∼200°C) leading to SiO2 films with O/Si ratio of ∼2.1. Moreover, the plasma ALD process led to a high conformality (95-100%) for trenches with aspect ratios of ∼30. In addition, the electronic (interface) properties of ultrathin ALD SiO2 films and ALD SiO2/Al2O3 stacks were studied by capacitance-voltage and photoconductance decay measurements. The interface quality associated with SiO2 was improved significantly by using an ultrathin ALD Al2O3 capping layer and annealing. The interface defect densities decreased from ∼1×1012 eV-1 cm-2 (at mid gap) for single layer SiO2 to < 1011 eV-1 cm-2 for the stacks. Correspondingly, ultralow surface recombination velocities < 3 cm/s were obtained for n-type Si. The density and polarity of the fixed charges associated with the stacks were found to be critically dependent on the SiO2 thickness (1-30 nm). [ABSTRACT FROM AUTHOR]

Although the next generation high-k gate dielectrics has been defined for the 45 nm complementary metal oxide semiconductor technology node, threshold voltage control and equivalent oxide thickness (EOT) scaling remain concerns for future devices. Therefore, the authors explored the effect of incorporating dysprosium in the gate stack. Results suggest that improved EOT-leakage scaling is possible by adding Dy to the interfacial SiO2 layer in a 1:1 ratio or by adding 10% Dy to bulk HfO2. The deposition of a 1 nm Dy2O3 cap layer lowered the threshold voltage by ∼250 mV. In addition, for future dynamic random access memory capacitor applications, dielectrics with [variant_greek_epsilon] of 50–130 are projected by the International Technology Roadmap for Semiconductors, unachievable with standard high-k dielectrics. Theoretical modeling can help direct the experimental work needed for extensive screening of alternative dielectrics. Moreover, materials such as perovskites only exhibit a sufficiently high-k value when properly crystallized. Therefore, control over the crystalline phase of the material might become a necessity to obtain the proper material characteristics as shown for SrTiOx. After crystallization, the permittivity was observed to increase from 20 to 135. In addition, material and gate stack optimization to limit leakage current densities for these higher-k dielectrics will be needed. [ABSTRACT FROM AUTHOR]