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A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

A closely coupled double-channel (DC) structure realized on an 8-inch GaN-on-Si wafer is utilized to fabricate GaN high-electron-mobility-transistors (HEMTs) with enhanced RF linearity. The strong channel-to-channel coupling from this DC structure enables efficient transport of electrons between the two parallel channels to accommodate balanced carrier concentration and current density between the two channels. Consequently, the nonlinearity of source resistance under high current operations and the external bias dependence of cut-off frequencies could be substantially mitigated, leading to device linearity enhancement. Meanwhile, the DC structure enables simple top gate control that favors a high-yield planar process. Two-tone measurements at 4 GHz show that the DC GaN HEMT delivers an output 3rd-order intermodulation point (OIP3) that is improved by 5.2 dB over a single-channel GaN HEMT. [ABSTRACT FROM AUTHOR]

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]

In this article, an ultrathin-barrier (UTB) AlGaN/GaN diode featuring metal–insulator–semiconductor (MIS)-gated hybrid anode (MG-HAD) and in situ Si3N4 cap passivation is demonstrated. The intrinsic turn-on voltage (VON) as low as 0.31 V determined by the as-grown AlGaN-barrier thickness (4.9 nm) is obtained and the VON exhibits excellent uniformity. More importantly, benefit from the MIS-gated hybrid anode structure, the UTB MG-HAD features good thermal stability in reverse blocking capability. The device delivers a substantially low leakage less than 1~μm/mm at −300 V at high temperature (HT) up to 200 °C, which is more than 100 × lower than that in the reference device w/o gate dielectric. Besides, the device exhibits respectably improved dynamic characteristics due to the incorporation of in situ Si3N4-cap passivation layer and remote plasma pretreatment (RPP) prior to Al2O3 gate dielectric deposition. The UTB MG-HAD featuring precisely VON modulation and low reverse leakage is of great interest for power electronic applications. [ABSTRACT FROM AUTHOR]

A new superjunction MOSFET (SJ-MOSFET) architecture with dual built-in Schottky diodes is proposed and studied with the numerical TCAD simulations. This letter is based on silicon. One Schottky contact is formed at the top of the n-pillar, while the other is formed at the bottom of the p-pillar. During the reverse conduction period, the Schottky junctions turn on at a lower voltage than the PN junction. The current flows through n-pillar and p-pillar in parallel, so the potential difference across the PN junction is kept below its turn-on voltage. Thus, minority carrier injection through the PN junction is completely suppressed, leading to a superior reverse recovery performance. Integration of a single Schottky contact to either the n-pillar or the p-pillar cannot completely suppress the turn-on of the PN junction in the SJ-MOSFET due to the potential drop created by the current through only one type of the pillars. Furthermore, the proposed dual-Schottky SJ-MOSFET reduces the gate charge (${Q} _{\mathrm {G}}$) and the gate-to-drain charge (${Q} _{\mathrm {GD}}$), compared with the conventional SJ-MOSFET, leading to better figures of merit. [ABSTRACT FROM AUTHOR]

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substratebias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the bufferrelated current collapse. [ABSTRACT FROM AUTHOR]

Dynamic ON-resistance ( \mathrm RON ) of 650-V GaN-on-Si lateral power devices with a floating Si-substrate termination is investigated. Compared with the grounded substrate termination, the floating substrate could deliver smaller dynamic \mathrm RON under higher drain bias (> 400 V) switching operation, but leads to larger dynamic \mathrm RON under low-drain bias (< 400 V). The underlying physical mechanisms are explained by the tradeoff between charge storage in the Si substrate and electron trapping effect in the GaN buffer layer. [ABSTRACT FROM AUTHOR]

The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic RON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$. While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic RON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

In this paper, we report the device performance of a high-voltage normally off Al2O3/GaN MOSFET on the Si substrate. Normally off operation is obtained by multiple cycles of O2 plasma oxidation and wet oxide-removal gate recess process. The recessed normally off GaN MOSFET with 3 \mum gate-drain distance exhibits a maximum drain current of 585 mA/mm at 9 V gate bias. The threshold voltage of the MOSFET is 2.8 V with a standard derivation of 0.2 V on the sample with an area of 2 \,\times\, 2 {\rm cm}^{2} . The gate leakage current is below 10^{-6}~{\rm mA}/{\rm mm} during the whole gate swing up to 9 V and the I{\scriptstyleON}/I{\scriptstyle OFF} ratio is larger than 10^{9} , indicating the good quality of Al2O3 gate insulator. The MOSFET with 10 \mum gate-drain distance shows a three terminal OFF-state breakdown voltage (BV) of 967 V at zero gate-source bias with a drain leakage current criterion of 1 \muA/mm . The specific ON-resistance $(R_{{{\scriptstyle {\rm ON}}},{\rm SP}}) of the device is 1.6 m\Omega\,\cdot\,cm^2 and the power figure of merit (BV^2/R{{\scriptstyle ON},SP}) is 584 MW/cm^2 . [ABSTRACT FROM AUTHOR]

High-Q copper inductors were fabricated on low-cost and low-loss bismaleimide triazine (BT) and glass substrate using electroplating process. A differential LC voltage-controlled oscillator (VCO) circuit was designed using these high-Q inductors at 2.4 GHz. Flip chip and multichip module (MCM) technologies were applied to assemble the active chips on BT and glass substrate. The inductors exhibited Q-factor as high as 25 at 2.4 GHz. VCOs with copper inductors on BT and glass substrate had phase noise of-108 dBc/Hz at 600 kHz offset for a 2.4-GHz carrier, which is 6-dB improvement compared with the one with on-chip Al inductors. There was almost no substrate loss for inductors on BT and glass substrates. The effect of fabrication defect and solder joint resistance were also investigated. This technique can be extended to other building blocks, thus realizing integration of the whole RF system. [ABSTRACT FROM AUTHOR]

This paper presents detailed characterization of a category of edge-suspended coplanar waveguides that were fabricated on low-resistivity silicon substrates using improved CMOS-compatible micromachining techniques. The edge-suspended structure is proposed to provide reduced substrate loss and strong mechanical support at the same time. It is revealed that, at radio or microwave frequencies, the electromagnetic waves are highly concentrated along the edges of the signal line. Removing the silicon underneath the edges of the signal line, along with the silicon between the signal and ground lines, can effectively reduce the substrate coupling and loss. The edge-suspended structure has been implemented by a combination of deep reactive ion etching and anisotropic wet etching. Compared to the conventional silicon-based coplanar waveguides, which show an insertion loss of 2.5dB/mm, the loss of edge-suspended coplanar waveguides with the same dimensions is reduced to as low as 0.5 dB/mm and a much reduced attenuation per wavelength (dB/λg) at 39 GHz. Most importantly, the edge-suspended coplanar waveguides feature strong mechanical support provided by the silicon remaining underneath the center of the signal line. The performance of the coplanar waveguides is evaluated by high-frequency measurement and full-wave electromagnetic (EM) simulation. In addition, the resistance, inductance, conductance, capacitance (RLGC) line parameters and the propagation constant of the coplanar waveguides (CPWs) were extracted and analyzed. [ABSTRACT FROM AUTHOR]

High-performance enhancement-mode AIGaN/GaN HEMTs (E-HEMTs) were demonstrated with samples grown on a low-cost silicon substrate for the first time. The fabrication process is based on a fluoride-based plasma treatment of the gate region and postgate annealing at 450 °C. The fabricated E-HEMTs have nearly the same peak transconductance (Gm) and cutoff frequencies as the conventional depletion-mode HEMTs fabricated on the same wafer, suggesting little mobility degradation caused by the plasma treatment. [ABSTRACT FROM AUTHOR]

In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70-μm-in diameter on 400-μm-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70-μm via, the inductance and resistance are measured to be 254 pH and 0.1 Ω, respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement. [ABSTRACT FROM AUTHOR]

We demonstrate high-voltage depletion-mode and enhancement-mode (E-mode) AlGaN/GaN high-electron-mobility transistors (HEMTs) on a GaN-on-silicon-on-insulator (SOI) platform. The GaN-on-SOI wafer features GaN epilayers grown by metal–organic chemical vapor deposition on a p-type (111) Si SOI substrate with a p-type (100) Si handle wafer. Micro-Raman spectroscopy significantly reveals reduced stress in the GaN epilayers, which is a result expected from the compliant SOI substrate. E-mode HEMTs fabricated by fluorine plasma implantation technique deliver high on/off current ratio (\10^8-\10^9), large breakdown voltage (1471 V with floating substrate), and low on-resistance (3.92 \m\Omega\cdot \cm^2). [ABSTRACT FROM PUBLISHER]

Vertical leakage/breakdown mechanisms in AlGaN/GaN high-electron-mobility transistors grown on low-resistivity p-type (111) Si substrate are studied by temperature-dependent current–voltage (I–V) measurements. It is found that the top-to-substrate vertical breakdown voltage (BV) is dominated by the space-charge-limited current conduction involving both acceptor and donor traps in the GaN buffer/transition layer. From the temperature-dependent transient backgating measurements, the acceptor level at EV + \543\ \meV and the donor level at EC-616 meV were identified. [ABSTRACT FROM AUTHOR]

We report the AlGaN-GaN high-electron mobility transistors (HEMTs) grown and fabricated on patterned silicon (111) substrates. A crack-free AlGaN-GaN HEMT heterostructure was grown on top of rectangular silicon ridges patterned on the silicon substrate. Fabrication of HEMT on the ridges was demonstrated using a polyimide planarization process. Maximum drain current density of 1.05 A/mm and peak transconductance of 150 mS/mm were achieved with 1.0 µm gate-length. The current gain cutoff frequency and maximum frequency of oscillation were 9.7 and 20.5 GHz, respectively, for the 1 µm × 300 µm devices. [ABSTRACT FROM AUTHOR]

Normally-off AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) on Si substrate were fabricated with the fluorine-based treatment technique. By employing a 20nmthick Al2O3 gate dielectric deposited by atomic layer deposition, the fabricated MOS-HEMT exhibits a large positive threshold voltage of + 3.5V, a maximum gate input voltage of 15V, a maximum saturate drain current of 5.3A and an off-state breakdown voltage of 402V. The high threshold voltage and the large input voltage swing is expected to improve the electromagnetic interference immunity and safety of AlGaN/GaN MOS-HEMT power switches. [ABSTRACT FROM AUTHOR]

Normally‐off AlGaN/GaN metal‐oxide‐semiconductor high electron mobility transistors (MOS‐HEMTs) on Si substrate were fabricated with the fluorine‐based treatment technique. By employing a 20nm‐thick Al2O3 gate dielectric deposited by atomic layer deposition, the fabricated MOS‐HEMT exhibits a large positive threshold voltage of + 3.5V, a maximum gate input voltage of 15V, a maximum saturate drain current of 5.3A and an off‐state breakdown voltage of 402V. The high threshold voltage and the large input voltage swing is expected to improve the electromagnetic interference immunity and safety of AlGaN/GaN MOS‐HEMT power switches. [ABSTRACT FROM AUTHOR]