Search

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

In this work, a memristor using Si nano-tip bottom electrode has been fabricated and evaluated. Compared with the control device fabricated in a planar structure, the invented Si nano-tip device statistically demonstrates 400 times of area shrinkage and 3 and 8 times of current reductions in the low- and high-resistance states, respectively, owing to the effects of highly confined switching area on the operations of multiple-weak-filament (MWF)-type memristor. The results reveal the validity of structural scaling on the MWF-type memristors as effective as a material approach. Moreover, the fabricated Si memristor has been evaluated as a synaptic device via pattern recognition toward neuromorphic applications in consideration of interconnect resistance. The proposed Si memristor shows substantially reduced inference power consumption by an increase in resistances and improved accuracy by 5% compared with the control device. [ABSTRACT FROM AUTHOR]

Modulation linearity of Si ring modulators (RMs) is investigated through the numerical simulation based on the coupled-mode theory and experimental verification. Numerical values of the key parameters needed for the simulation are experimentally extracted. Simulation and measurement results agree well. With these, the influence of input optical wavelength and power on the Si RM linearity are characterized. [ABSTRACT FROM AUTHOR]

We present a custom-designed integrated circuit (IC) implemented in 0.25-μm BiCMOS technology that can automatically control the Si micro-ring modulator (MRM) temperature for optimal modulation characteristics. The IC monitors the optical modulation amplitude (OMA) of an Si MRM and provides the optimal heater setting for the maximum OMA. The IC consists of trans-impedance amplifier, power detector, track-and-hold circuit, comparator, digital-to-analog converter, and digital controller, all of which are integrated in a single chip. We demonstrate that, with this IC, an Si MRM can provide the maximum OMA for 25-Gb/s operation despite changes in temperature and input optical power. [ABSTRACT FROM AUTHOR]

In this paper, a novel vertical-structured electron-hole bilayer tunnel field-effect transistor (V-EHBTFET), which features dual gates located at each side of Si fin, is proposed and its electrical characteristics are examined by a technology computer-aided design simulation depending on device parameters. Comparing with the conventional EHBTFET, V-EHBTFET shows a comparable performance in terms of subthreshold swing, OFF- and ON-state currents, and turn-ON voltage with much higher scalability with the help of a novel device architecture. An exemplary self-aligned process flow is also proposed. [ABSTRACT FROM AUTHOR]

Monolithic three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated. This is the first experimental demonstration of 65-nm M3D CMOS-NEM RL circuits satisfying the 1.2-V supply voltage ( V\mathsf {DD} ) requirement of the 65-nm technology node. The fabrication process is identical to the conventional 65-nm CMOS baseline process, in which copper NEM memory switches are formed by a dual damascene process. [ABSTRACT FROM AUTHOR]

We present a linear equivalent circuit model for the depletion-type Si microring modulator (MRM). Our model consists of three blocks: one for parasitic components due to interconnects and pads, one for the electrical elements of the core p-n junction, and the third for a lossy LC tank representing Si MRM optical modulation characteristics. Model parameter values are extracted from measurement of a fabricated Si MRM device. Simulated modulation characteristics with our equivalent circuit show very good agreement with measured results. Using our model, we can analyze Si MRM modulation frequency response characteristics and perform gain-bandwidth product optimization of the entire Si photonic transmitter composed of a Si MRM and electrical driver circuits. [ABSTRACT FROM AUTHOR]

The influence of self-heating on the static transmission characteristics of depletion-type Si micro-ring modulators (MRMs) is investigated. Self-heating, caused by free-carrier absorption of the input light inside the doped ring waveguide, increases the effective refractive index of the ring waveguide and results in the red-shifted resonance wavelength. This phenomenon is modeled based on the coupled-mode equation with a newly-introduced self-heating coefficient R. The accuracy of our model is confirmed by measurement. In addition, dependence of R on device size and doping concentration is experimentally investigated and the resulting dependence is explained. [ABSTRACT FROM PUBLISHER]

The hump effects of germanium/silicon heterojunction tunnel field-effect transistors are discussed. Simulation results show that they are originated when indirect band-to-band tunneling is converted into direct one as gate voltage ( Vg ) increases. In order to suppress the hump effects, two ideas are proposed. First, the length of intrinsic-germanium channel ( L\mathrm{ Ge} ) is optimized using a novel process flow. Second, gate-to-channel coupling is improved by increasing source doping concentration ( NS ). [ABSTRACT FROM AUTHOR]

An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}} ) than a conventional planar TFET with the same gate overdrive ( V\mathrm{ov} ) of 0.8 V, due to improved subthreshold swing ( S ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed. [ABSTRACT FROM AUTHOR]

The authors present a low‐power 850 nm Si optoelectronic integrated circuit (OEIC) receiver fabricated in standard 65 nm complementary metal–oxide semiconductor (CMOS) technology. They analyse power consumption of previously reported CMOS OEIC receivers and determine the authors receiver architecture for low‐power operation. Their OEIC receiver consists of a CMOS‐compatible avalanche photodetector and electronic circuits that include an inverter‐based transimpedance amplifier, a tunable equaliser and a post amplifier. With the fabricated OEIC receiver, they successfully demonstrate 8 Gb/s operation with a bit‐error rate <10−12 at incident optical power of −4.5 dBm. Their OEIC receiver consumes 5 mW with 1.2 V supply voltage. To the best of their knowledge, their OEIC receiver achieves the lowest energy efficiency among 850 nm CMOS OEIC receivers. [ABSTRACT FROM AUTHOR]

We investigate the area-dependent characteristics of photodetection frequency responses of 850-nm silicon avalanche photodetectors (APDs) fabricated with standard complementary metal–oxide–semiconductor (CMOS) technology. CMOS-compatible APDs (CMOS-APDs) based on a \p^+/n-well junction with four different device areas are used for the investigation, and we identify factors that influence photodetection frequency responses with the goal of achieving optimal photodetection bandwidth performance. Their current–voltage characteristics, electrical reflection coefficients, and photodetection frequency responses are measured, and the characteristics of the CMOS-APD photodetection frequency responses are analyzed using equivalent circuit models. From this, it is clarified how the four different factors of photogenerated-carrier transit time, device RC time constant, inductive-peaking effect, and parasitics contribute to the photodetection frequency responses and how their contribution changes with device areas. Among the four types of CMOS-APDs investigated in this study, the \10 \times \10\ \mu\m^2 CMOS-APD has the largest 3-dB photodetection bandwidth of 7.6 GHz. [ABSTRACT FROM AUTHOR]

This letter discusses the effects of device geometry, such as channel layer thickness and multiple-gate structure on hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). According to simulation results, contrary to conventional TFETs or MOSFETs, HG TFETs show improved subthreshold swing (SS) for increasing channel thickness or decreasing number of gates. The trend with on-current ION depends on operating voltage VDD. [ABSTRACT FROM AUTHOR]

We investigate the effects of guard-ring (GR) structures on the performance of silicon avalanche photodetectors (APDs) fabricated with the standard complementary metal–oxide-semiconductor (CMOS) technology. Four types of CMOS-compatible APDs (CMOS-APDs) based on the \p^+/ \n-well junction with different GR structures are fabricated, and their electric-field profiles are simulated and analyzed. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth for CMOS-APDs are measured and compared. It is demonstrated that the GR realized with shallow trench isolation provides the best CMOS-APD performance. [ABSTRACT FROM PUBLISHER]

We present an equivalent circuit model for CMOS- compatible avalanche photodetectors. The equivalent circuit model includes an inductive component for avalanche delay, a current source for photogenerated carriers, and several components that model the device structure and parasitic effects. The model provides accurate impedance characteristics and photodetection frequency responses. [ABSTRACT FROM AUTHOR]

The authors report silicon avalanche photodetectors (APDs) fabricated with 0.18 μm standard complementary metal-oxide-semiconductor (CMOS) process without any process modification or a special substrate. When the bias is above the avalanche breakdown voltage, CMOS-compatible APD (CMOS-APD) exhibits negative photoconductance in photocurrent-voltage relationship and rf peaking in the photodetection frequency response. The reflection coefficient measurement of CMOS-APD indicates that rf peaking is due to resonance caused by appearance of inductive components in avalanche region. The rf-peaking frequency increases with the increasing reverse bias voltage. [ABSTRACT FROM AUTHOR]