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Focuses on a study of process-induced mechanical stress in isolation structures by means of micro-Raman spectroscopy. Methods used for the preparation of the poly-buffered local oxidation of silicon samples; Optical Raman modes of crystalline silicon; Analysis of stress due to the silicon nitride mask.

Abstract: When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing. [Copyright &y& Elsevier]

In this paper, three techniques are discussed that provide information on process-induced local mechanical stress in silicon: the convergent beam electron diffraction technique of transmission electron microscopy, X-ray micro-diffraction and micro-Raman spectroscopy. We discuss the principles of these techniques, their spatial resolution, the ease-of-use, the information that can be obtained, the required sample preparation, the measurement time, and the complementarities of these techniques. We demonstrate this for stress induced by shallow trench isolation and correlate the results to finite element analysis results. [Copyright &y& Elsevier]

We report a differential scanning photocapacitance microscopy technique based on the detection of light-induced capacitance changes allowing mapping of metal interconnection line defects in through-silicon-via (TSV) structures used in three-dimensional (3-D) integration technology. Due to the photosensitive silicon depletion capacitance, observation of the photocapacitance response enables non-destructive two-dimensional (2-D) visualization of metallization line ruptures in TSV structures. We demonstrate the application of the proposed method on a TSV chain structure and reveal the location of the open metallization rupture. [ABSTRACT FROM AUTHOR]

Self-aligned assembly, making use of capillary forces, is considered as an alternative to active alignment during thermo-compression bonding of Si chips in the 3D heterogeneous integration process. Various process parameters affect the alignment accuracy of the chip over the patterned binding site on a substrate/carrier wafer. This paper discusses the chip motion due to wetting and capillary force using a transient coupled physics model for the two regimes (that is, wetting regime and damped oscillatory regime) in the temporal domain. Using the transient model, the effect of the volume of the liquid and the placement accuracy of the chip on the alignment force is studied. The capillary time (that is, the time it takes for the chip to reach its mean position) for the chip is directly proportional to the placement offset and inversely proportional to the viscosity. The time constant of the harmonic oscillations is directly proportional to the gap between the chips due to the volume of the fluid. The predicted behavior from transient simulations is next experimentally validated and it is confirmed that the liquid volume and the initial placement affect the final alignment accuracy of the top chip on the bottom substrate. With statistical experimental data, we demonstrate an alignment accuracy reaching <1 μm. [ABSTRACT FROM AUTHOR]

The in-plane stress distribution in copper through silicon vias (TSV) ensembles of different design has been studied by the scanning infrared stress explorer (SIREX). SIREX is a reflection-based plane polarimeter particularly developed for the high-resolution stress state visualization in silicon-based electronic and mechanic devices. The SIREX method is based on the principle of stress-induced birefringence. We demonstrate that the silicon crystal matrix around the TSV is optically anisotropic with a stress distribution being similar to fields which are known from point-like stress sources. The maps of optical anisotropy have been converted into maps of difference of principal stress components Δσ with a resolution of a few kPa. We show that magnitude and direction of Δσ depend on the geometrical design of the TSV, in particular on length and diameter. The average radial profile of magnitude is discussed. In consequence, we offer a promising tool and method for the non-destructive evaluation of TSV structures in view of their stress characteristics and integrity. [ABSTRACT FROM AUTHOR]

Highlights: [•] Analytical modelling, FEM simulations and 4 point bending for BEOL strength analysis. [•] Reduced low-k stiffness results in exponential growth of stress in Cu via’s. [•] Keep-out-zones around copper through silicon via’s are defined. [Copyright &y& Elsevier]

Abstract: In this paper, the degradation of a GaN-on-Si based RF power amplifier is investigated by means of electrical characterization. The reliability issues identified during this work are clearly related to the high thermal resistance between the device and the heat sink, which causes gate-leakage current and output power degradation. Moreover, we have demonstrated a low cost thermal optimization approach by increasing the thermal dissipation area and reducing the device carrier thickness. Measurement results show that the saturated output power can be increased from 1W up to 5W without device degradation at 3.8GHz. [Copyright &y& Elsevier]