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The ionic properties of a metal-coated silicon nanopore were examined in a nanofluidic system. We observed a strong increase of the ionic noise upon laser light illumination. The effect appeared to be strongly mediated by the resonant excitation of surface plasmons in the nanopore as was demonstrated by means of ionic mapping of the plasmonic electromagnetic field. Evidence from both simulations and experiments ruled out plasmonic heating as the main source of the noise, and point toward photoinduced electrochemical catalysis at the semiconductor-electrolyte interface. This ionic mapping technique described is opening up new opportunities on noninvasive applications ranging from biosensing to energy conversion.

In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (${L}_{g}$) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because of the absence of short-channel effects and of a subthreshold-slope limit. As a solution to the low on-currents of silicon-based TFETs, the incorporation of silicon-germanium at the source-channel interface has been considered. However, the understanding of the band-to-band-tunneling mechanism at heterojunctions is incomplete. We have investigated through device simulations and modeling the impact of source-material modifications on the tunnel current in n-channel nanowire TFETs. Our modeling work includes the development of a semi-analytical model, which determines the tunnel probability along the dominant tunnel path in two-dimensional TFETs. In particular, we have analyzed the impact of the bandgap, electron affinity, effective mass, dielectric constant, and density of states of both source and channel material. We show that a small-bandgap source material and a large positive electron-affinity offset at the source-channel interface boost the tunnel current of n-channel TFETs. [ABSTRACT FROM AUTHOR]

A comprehensive study of different fundamental aspects of light emission from defects in Si semiconductor devices is presented. Based on an experimental analysis, using a new highly sensitive spectroscopic photon emission microscope (SPEM) for continuous wavelength analysis (2.5 eV-1.2 eV), a unique assignment of the spectrum of the emitted light and the corresponding failure mechanism is established. Three distinguishable basic spectral categories were identified. They were attributed to gate oxide breakdown, metal shorts, and electro-static discharge caused junction spiking. The focused ion beam technique was used to look at the damage sites for confirmation of the SPEM results. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Presents a study that characterized substrate hot-hole injection induced hole trapping and interface trap generation. Temperature by which the characterization was made; Independence of the trapping from injection conditions in the silicon; Insensitivity of the trapping to the oxide field; Rate of initial trapping efficiencies.

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential. [ABSTRACT FROM AUTHOR]

To get a better insight into the vertical leakage mechanism of GaN-on-Si, the carrier transport from n+, n, p+, and p-Si(111) substrates through the AlN nucleation layer was investigated. A plateau in the current-voltage curve was found only for the AlN/p-Si heterojunction due to depletion of the p-Si substrate. Detailed study illustrated that it was the leaky AlN that cannot effectively block the increasing amount of electrons in the inversion layer at the interface and triggered the depletion. Temperature-dependent characterization suggested that the forward vertical leakage mechanism of AlN/Si could be explained sequentially by Ohm’s law, space-charge-limited conduction, variable-range hopping, and trap-assisted tunneling. A model involving shallow donor traps, interface traps, and deep level traps was proposed to explain the leakage characteristics. This paper shows that the carrier concentration of the Si substrates strongly impacts the vertical leakage characteristics, and also that the carrier transport from the Si substrate through the AlN nucleation layer is heavily influenced by traps. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) hafnium oxide is a promising candidate for memory applications. In this paper, endurance, imprint, and retention tests are carried out on FE aluminum-doped hafnium oxide thin films with different electrodes: 1) metal–insulator–metal (MIM) and 2) silicon–insulator–silicon(SIS). MIM devices exhibit higher endurance than SIS devices. However, SIS devices show superior imprint and retention, with an extrapolated retention time-to-failure larger than 10 years at 85 °C. These results are very promising to integrate FE-HfO2 in 3-D structures, either for dynamic random access memory or for NAND applications. [ABSTRACT FROM PUBLISHER]

Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved. This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size. [ABSTRACT FROM AUTHOR]

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 ^\circC ; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev , when neutral, lift well above Ev after charging, and return below Ev following neutralization. [ABSTRACT FROM PUBLISHER]

This paper presents a new integration scheme to fabricate a Si/Si0.55~Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-\mum gate length device shows on current in excess of 20 \muA/\mum at VGS=VDS=1.2~\rm V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by \sim0.35~V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration. [ABSTRACT FROM AUTHOR]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a \SiO2/ \HfO2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups. [ABSTRACT FROM PUBLISHER]

This paper studies the impact of high-mobility materials on the performance and energy efficiency of near- and sub-threshold CMOS logic circuits by means of analytical equations and experimental data on SiGe pMOSFETs. The introduction of high-mobility materials is shown to improve the energy-performance trade-off in near-threshold circuits more than in above-threshold circuits, since the benefits of higher mobility are degraded at higher longitudinal and transversal electric fields. On the other hand, results show that high-mobility materials do not exhibit any advantage in terms of the energy-performance trade-off in sub-threshold logic circuits. This is explained by the fact that the benefits brought by the larger mobility of SiGe or other alternative materials can be obtained by tuning the threshold voltage of conventional Si devices. [ABSTRACT FROM AUTHOR]

We report extensive experimental results of the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The results clearly show that this high-mobility channel technology offers significantly improved NBTI robustness compared with Si-channel devices, which can solve the reliability issue for sub-1-nm equivalent-oxide-thickness devices. A physical model is proposed to explain the intrinsically superior NBTI robustness. [ABSTRACT FROM AUTHOR]

The time-dependent variability of nanoscaled \Si0.45 \Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as \1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology. [ABSTRACT FROM AUTHOR]

The ESD robustness of GaN-on-Si Schottky diodes is investigated using on-wafer HBM and TLP. Both forward and reverse diode operation modes are analyzed as a function of device geometry, which strongly impact the corresponding failure mechanism. In forward mode, the anode-to-cathode length reduction and the total device width increase are beneficial for ESD robustness; however, in reverse mode, the ESD robustness does not depend on the total device width and saturates at around 400 V for medium and long anode-to-cathode lengths. The corresponding failure mechanisms are respectively attributed to the current distribution and Si substrate breakdown under forward and reverse mode ESD stresses. [ABSTRACT FROM PUBLISHER]

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of \Si/SiO2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI. [ABSTRACT FROM AUTHOR]

In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high-\kappa/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lower leakage of the Si technology. Appropriate circuit- and system-level metrics are introduced to identify the advantages offered by SiGe technology in VLSI circuits. Analysis is performed in the context of next-generation VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efficiency through aggressive voltage scaling, other than low-leakage techniques. Analysis shows that the SiGe technology has more efficient leakage-delay and dynamic energy-delay trade-offs at nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis performed at nominal supply actually underestimates the benefits of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems. [ABSTRACT FROM PUBLISHER]

We develop a model for the tunnel field-effect transistor (TFET) based on the Wentzel-Kramer-Brillouin approximation which improves over existing semi-classical models employing generation rates. We hereby introduce the concept of a characteristic tunneling length in direct semiconductors. Based on the model, we show that a limited density of states results in an optimal doping concentration as well as an optimal material's band gap to obtain the highest TFET on-current at a given supply voltage. The observed optimal-doping trend is confirmed by 2-dimensional quantum-mechanical simulations for silicon and germanium. [ABSTRACT FROM AUTHOR]

50 MeV and 80 MeV neutron-induced failure is investigated for several types of power devices (super-junction, IGBT and SiC) from different vendors. A strong dependence on the device type and orientation is observed. [ABSTRACT FROM AUTHOR]

Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge at 0.66 eV is considered. However, direct band-to-band tunneling (BTBT) in Ge should be included in tunnel FET modeling and simulations since the energy difference between the Ge conduction band edges at the L and \Gamma valleys is only 0.14 eV at room temperature. In this paper, we theoretically calculate the parameters A and B of Kane's direct and indirect BTBT models at different tunneling directions ([100], [110], and [111]) for Si, Ge and unstrained \Si1-x\Gex. We highlight how the direct BTBT component becomes more important as the Ge mole fraction increases. The calculation of the band-to-band generation rate in the uniform electric field limit reveals that direct tunneling always dominates over indirect tunneling in Ge. The impact of the direct transition in Ge on the performance of two realistic tunnel field-effect transistor configurations is illustrated with TCAD simulations. The influence of field-induced quantum confinement is included in the analysis based on a back-of-the-envelope calculation. [ABSTRACT FROM AUTHOR]

Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8- \\rm\AA EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-\\rm \AA EOT device. Clear charge pumping currents are obtained on the 5.8- \\rm\AA EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-\\rm\AA EOT device is found to be higher than that in the 10.1- \\rm\AA EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2 \\rm\AA inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8- \\rm\AA EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1- \\rm\AA EOT device. The bulk trap Not generated after stress is higher in the 5.8- \\rm\AA EOT device due to the higher initial bulk trap density. [ABSTRACT FROM AUTHOR]

The off-state degradation of n-channel laterally diffused metal–oxide–semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an \n^+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both off-state and ESD reliability. [ABSTRACT FROM AUTHOR]

A new design methodology for FinFET devices is presented, which takes into account all complex dependences on both layout and process parameters of the electrostatic discharge (ESD) electrical device parameters of NMOS FinFET devices operating in parasitic bipolar mode. This methodology allows optimization toward a given ESD target (area consumption, leakage current, voltage drop, parasitic capacitance, etc.) while fulfilling several imposed design constraints. Fundamental insights are obtained regarding the different design and device tradeoffs. [ABSTRACT FROM PUBLISHER]

One of the fundamental questions for gate-stack scaling is whether the low-field mobility measured in long-channel devices is a good proxy for short-channel performance at high field. In this paper, we thoroughly investigate low- and high-field transports (velocity and mobility) in 1-nm-EOT high-κ materials on Si (100) and (110) down to cryogenic temperature. It is shown that scattering in Si substrate dominates the transport at high field, thus enabling relaxation of the low-field-mobility requirement for future scaling below 1-nm EOT. [ABSTRACT FROM AUTHOR]

As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an inverter and competing with the MOSFET. We have investigated the heterostructure TFET with respect to complementarity based on our semianalytical model, and we propose the In~Ga1~As-source silicon-TFET as p-TFET. This design is partitularly applicable to nanowire-based transistor architectures. We discuss the complementarity of the I-V curves, and we analyze the threshold voltage behavior of the complementary TFETs. [ABSTRACT FROM AUTHOR]

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability ΔVth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates ΔVth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of ΔVth is clarified. [ABSTRACT FROM AUTHOR]

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs. [ABSTRACT FROM AUTHOR]

A comparative study of the reliability issues of triple-gate and planar FETs processed on the same silicon-on-insulator wafer is presented. It is shown that the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown (BD) for different gate voltages and temperatures. The apparent higher Weibull slope observed in planar devices with respect to the triple-gate devices is ascribed to the area dependence of the time-to-BD detection. In spite of the different surface orientations, low-frequency noise measurements indicate similar values of the interface trap density for triple-gate and planar FETs. [ABSTRACT FROM AUTHOR]

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3/GeO2/Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise. [ABSTRACT FROM PUBLISHER]

We propose a novel metal/silicon/metal (MSM) selector using ultrathin (<10~nm) undoped amorphous silicon (a-Si) for resistive-RAM selector application. The new selector behaves as a bidirectional diode, showing a high current drive (\sim2.2~MA/cm)^2, high selectivity (\sim240 for 1/2 bias), fast switching speed (<1~ns), and excellent endurance (>10^8~cycles at target drive current). The doping-free a-Si structure alleviates the dopant-induced variability concerns for ultrascaled devices and eliminates the need for a dopant-activation anneal. Circuit simulations show feasibility of 1-Mb array, with over 25% read margin and 70% write margin, when using the new MSM structure as a selector for a HfO2-based resistive switching memory element. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45^\circ rotated devices compared with the 0^\circ rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45^\circ rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv—exhibited when transitioning from planar to FinFET architecture at 45^\circ rotation—plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45^\circ rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho [ABSTRACT FROM AUTHOR]

\TiN/Hf/HfO2/\poly-Si structure was employed as the platform to investigate the resistive switching mechanism of metal–insulator-semiconductor (MIS)-based resistive random access memory (RRAM) devices. Based on the presence of a \HfSiOx interfacial layer containing a large amount of oxygen vacancy defects, a resistive switching model is proposed to explain the observed bipolar switching behavior which is of opposite operation polarity as compared to metal-insulator-metal (MIM)-based \TiN/Hf/HfO2/\TiN RRAM devices. The dependence of dopant type/concentration on operation voltage is explained by depletion/accumulation effect of poly-Si bottom electrode. In addition, the MIS-based RRAM devices exhibit good reliability performance in terms of stable dc switching endurance up to 100 cycles and ten-year retention ability at 85 ^\circ\C, with memory window higher and close to 100, respectively. The results suggest that MIS-based RRAM using \Hf/HfO2 is a promising alternative for next-generation nonvolatile applications. [ABSTRACT FROM PUBLISHER]

The reliability of ultra-thin silicon oxynitride gate dielectrics was investigated in terms of the Weibull slope of the tbd distributions, and the voltage acceleration factor. High field tBD statistics were extrapolated using a worst-case linear fit, to the low field region. The samples showed low voltage acceleration, which degrades reliability, but this is overcome by high Weibull slopes (β), which improve reliability. The high β values were investigated by monitoring the change in β as gate current increased during CVS. We saw the Weibull slope change from &ap;1 at low current to 2 at high current, indicating that breakdown results from 2-trap conduction. Charge pumping measurements showed that the trap generation rate at the SiON/Si interface, where most of the Nitrogen resides was very low. Thus it was concluded that there is a much higher trap generation rate in the bulk than at the interface and this is responsible for the values of β. [Copyright &y& Elsevier]