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A p-channel metal–ferroelectric–insulator–silicon field-effect transistor (FET) with a 300-nm-thick \SrBi2\Ta2\O9 (SBT) ferroelectric film and a 10-nm-thick HfTaO layer on silicon substrate was fabricated and characterized. The device shows a nearly unchanged memory window of about 0.9 V after a \2 \times \10^11-cycles fatigue test, an on/off current ratio of more than \10^7, and a field-effect mobility of approximately 42 \cm^2/\V \cdot \s. Moreover, a drain-current on/off ratio as high as \10^5 was obtained with a fixed gate voltage of 2.5 V after over a \10^5-s elapsed time without any obvious degradation. These results may suggest that the Pt/SBT/HfTaO/Si FET is suitable for high-performance ferroelectric memory. [ABSTRACT FROM AUTHOR]

A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao–Sah integral is carried out to obtain the drain current. It is shown that the model is in good agreement with numerical simulations from subthreshold to saturation region. Finally, we discuss the strengths and limitations (i.e., threshold voltage shifts) of the JLFET, which has been recently proposed as a promising candidate for the JFET. [ABSTRACT FROM AUTHOR]

During heavy-ion experiments, the single-event gate rupture (SEGR) effects can still be observed in the vertical double-diffused power MOSFET (VDMOS) with radiation-hardened cells. Fault analysis demonstrates that the hot spots locate at the termination of the VDMOS. Then, several mitigation solutions for termination structure are discussed comprehensively by means of TCAD simulations. Finally, a combined hardness method with horizontally extending P+ region and adding floating N+ region is proposed. It is effective to reduce the electric field of gate oxide to below the calculated critical field, without additional masks and process steps. [ABSTRACT FROM AUTHOR]

By applying non-equilibrium molecular dynamics simulation, it is demonstrated that the thermal conductivity of the reported Si/Ge core-shell nanowires (NWs) can be further reduced by shell doping. The thermal conductivity of Si/Ge0.6Si0.4 core-shell NWs is only about 66% of that of Si/Ge core-shell NWs. By analyzing the participation ratios of eigenmodes, it is revealed that the large reduction in the thermal conductivity of Si/Ge0.6Si0.4 core-shell NWs stems from the strong localization of the phonon modes from 1.0 THz to 2.0 THz and the modes from 9.0 THz to 16.0 THz due to both impurity scattering and interface scattering associated with peculiar structure of shell doped silicon NWs. [ABSTRACT FROM AUTHOR]

Abstract: The total ionizing dose (TID) radiation effects of partially-depleted (PD) silicon-on-insulator (SOI) devices fabricated in a commercial 0.2µm SOI process were investigated. The experimental results show an original phenomenon: the “ON” irradiation bias configuration is the worst-case bias for both front-gate and back-gate transistors. To understand the mechanism, a charge distribution model is proposed. We consider that the performance degradation of the devices is due to the radiation-induced positive charge trapped in the bottom corner of Shallow Trench Isolation (STI) oxide. In addition, by comparing the irradiation responses of short and long channel devices under different drain biases, the short channel transistors show a larger degeneration of leakage current and threshold voltage. The dipole theory is introduced to explain the TID enhanced short channel effect. [Copyright &y& Elsevier]

Abstract: The pseudo-MOS transistor is a quick and effective technique for characterizing the electrical properties of silicon-on-insulator (SOI) wafer. We investigated the total ionizing dose (TID) response of pseudo-MOS transistors fabricated on SOI wafers hardened by single or multiple step Si ion implantation. It is demonstrated that the two Si ion implantation methods can both improve the radiation hardness of SOI wafers owing to the generation of deep electron traps in the buried oxide (BOX). However, the lattice damage of top silicon film caused by the single step implantation compared with the multiple degenerates the electrical properties of transistors, especially for the sub-threshold swing. The high resolution transmission electron microscopy (HRTEM) was used to observe the lattice quality. [Copyright &y& Elsevier]