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As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. [ABSTRACT FROM AUTHOR]

The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry. When a radiation particle strikes a sensitive node of a conventional 6T SRAM cell, a single event upset (SEU) can occur, flipping in the stored data in the cell. Additionally, charge sharing between transistors can cause single-event multi-node upsets (SEMNUs), where data in multiple nodes are flipped simultaneously due to a single particle strike. Therefore, this paper proposes a radiation-hardened high stability 16T (RHHS16T) cell for space applications. The characteristics of RHHS16T are evaluated and compared with previously proposed radiation-hardened SRAM cells such as QUCCE12T, WEQUATRO, RHBD10T, RHD12T, RSP14T, RHPD14T, and RHBD14T. Simulation results for RHHS16T indicated that the proposed cell demonstrates improved performance in read stability, write access time, and write stability compared to all comparison cells. These improvements in the proposed cell are achieved with higher power consumption and a minor area penalty. Notably, isolating the storage node from the bit line during read operations and the feedback loop between nodes during write operations enables the proposed RHHS16T to achieve enhanced read stability and write stability, respectively. The proposed integrated circuit was implemented using a 90 nm CMOS process and operates at a supply voltage of 1V. Furthermore, RHHS16T provides high immunity against SEUs and SEMNUs. Through its enhanced read and write stability, it ensures reliable data retention for space applications. [ABSTRACT FROM AUTHOR]

As the progress of technology continues in accordance to Moore's law, the density and downsizing of circuitry presents a significant vulnerability to the effects of soft errors. This study proposed a novel method to mitigate soft errors by increasing the robustness of complementary metal oxide semiconductor (CMOS) technology against soft errors via the use of transmission gates within the memory nodes of static random access memory (SRAM) which functioned as a low pass filter that disallowed the occurrence of data corruption. The proposed SRAM was tested against parameter variation of supply voltage and temperature. The critical charge was observed to increase with supply voltage increase, with the opposite being true of the increase in temperature. The increase in critical charge of up to 88.63% was achieved with regards to parameter variation for the transmission gate SRAM in comparison to the 6T SRAM. [ABSTRACT FROM AUTHOR]

Summary: Static Random Access Memory (SRAM) is vital in aerospace applications, but it may experience soft errors in strong radiation environments. This paper proposes a reconfigurable radiation SRAM with two operating modes catering to different environmental requirements: (1) traditional triple modular redundancy mode used when the radiation environment is strong and (2) SRAM cell expansion mode used when the radiation is not very strong. For example, when the memory capacity of a single module is 8 k, the memory capacity is 8 k in traditional triple modular redundancy mode, but it can be tripled to 24 K in extended mode. As can be obviously seen, this design can adjust the size according to the needs. In SRAM cell expansion mode, the proposed 14T SRAM cell enables the memory to maintain radiation resistance. Compared with DICE, RHBD‐12T, and WHIT, the read speed is improved by 3.8%, 5.7%, and 11.5% respectively, but compared with WE‐QUATRO, the read speed is reduced by 1.9%. The hold static noise margin is 1.378 times than DICE, 1.201 times than WE‐QUATRO, 1.045 times than RHBD‐12T, and 1.14 times than WHIT, respectively. The proposed 14T cell in this paper exhibits the highest critical charge value compared with the other cells. Combined with the expansion mode of the reconfiguration design, it shows great stability. [ABSTRACT FROM AUTHOR]

In this paper, a 12-transistor radiation tolerant SRAM cell has been proposed in 16-nm CMOS predictive technology model. The proposed 12T SRAM cell offers higher immunity to soft error than all other compared memory cells. The proposed SRAM cell proves its robustness against radiation strike by showing the largest amount (4.1 fC) of critical charge (QC) among all the comparison SRAM cells. The proposed 12T cell consumes 48.03%, and 48.68% lower hold power than QUCCE 12T and QUCCE 10T SRAM cell, respectively. It exhibits 79.92%, 33.77%, 84.84%, and 59.97% shorter read delay compared to 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively at a nominal supply voltage of 0.7 V. In terms of write delay the proposed 12T exhibits 68.49% shorter write delay as compared with QUCCE 10T. The proposed circuit has higher RSNM as compared to other SRAM cells and consumes lesser silicon area than other comparison cells except 6T and QUCCE 10T SRAM cell. The read stability of proposed 12T is 3.10×, 1.76×, 2.09×, 1.62 × times higher than 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively. The proposed 12T exhibits 65.85%, 41.46%, 26.82%, and 41.46% improvement in critical charge (QC) in comparison with 6T SRAM, QUCCE 10T, WE QUATRO and QUCCE 12T, respectively. However, these improvements are achieved at the cost of marginal degradation of write margin as compared to 6T, QUCCE 10T, WE QUATRO and QUCCE 12T SRAM cells, respectively. In terms of area, the proposed 12T acquires lesser area as compared to QUCCE 12T (6.32%) and WE QUATRO (12%). Hence, the proposed 12T SRAM cell is a promising selection for future highly reliable terrestrial applications. [ABSTRACT FROM AUTHOR]

Numerous soft faults in SRAM memory emerge as technological innovations scales down, resulting in single and several cell upsets. The increased use of transistors in space applications has rendered semiconductor devices more vulnerable to soft errors caused by harm from radiation. A single event upset (SEU) is occurring whenever a soft error produces a tiny bit flipped in a storage device. Because SEU faults affect system performance, they must be addressed as soon as possible. Error-correcting codes, like the method known as (7,4) hamming codes, were devised and their decoding and encoding procedures were verified. It also used to detect single errors that can be fixed. It also helps detect double errors, SECDED however repair of double errors is tough. The decoding and encoding techniques of these approaches were investigated, and all computational findings had been verified and executed in a Xilinx NEXYS 4 DDR FPGA board. [ABSTRACT FROM AUTHOR]

This work studies radiation-induced effects in FinFET technology, the leading technology in advanced nodes for high-end embedded systems. As the fin height (HFIN) and the number of fins (NFIN) are two critical parameters in the development of newer technologies, the soft-error robustness to radiation-induced effects in FinFET SRAM cells with HFIN and NFIN) is evaluated using Technology Computer-Aided Design (TCAD) tools. The ion strike direction and the process variations are considered. An analytical method to evaluate the failure probability of the memory cell due to radiation-induced effects under process variations is proposed. The amount of critical and collected charges of the memory cell are obtained with TCAD tools. The proposed method can be used to get insight into the robustness behavior of the memory cell with HFIN and NFIN and to guide the obtention of HFIN and NFIN parameters in developing new FinFET technologies. [ABSTRACT FROM AUTHOR]

The impact of 0.1–10 MeV neutron-induced single-event upsets (NSEUs) on terrestrial SER (soft error rate) prediction is analyzed for several broad spectrum neutron sources based on 0.1–200 MeV NSEU energetic-dependent cross-sectional data of a 40 nm SRAM. The results show that for test facilities with abundant <10 MeV neutrons, such as ISIS ChipIR, J-PARC BL10, CSNS Back-n, and CSNS BL09, the terrestrial SER is overestimated. The overestimation could reach 78%–287%. By reducing the cutoff energy (Emin) from 10 to 6 MeV, the overestimation can be decreased. However, the overestimation can still reach up to 164% in this case, significantly larger than the results reported by previous studies. By analyzing the contribution of neutrons in different energy bins to NSEUs, the discrepancy is proved to be attributed to the sensitivity of NSEUs to 0.1–1 MeV neutrons, along with the overpopulation of 0.1–1 MeV neutrons for certain test facilities, such as ISIS ChipIR and CSNS BL09. Therefore, it is necessary to take 0.1–1 MeV NSEU sensitivity into account when studying the prediction method using broad spectrum neutron sources. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

Summary: As the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations. [ABSTRACT FROM AUTHOR]

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit. [ABSTRACT FROM AUTHOR]

SRAM cells in spacecraft or space stations are susceptible to single event upset (SEU) caused by high-energy particle impacts. Conventional 6 T SRAM cells are more prone to soft errors in this environment. In this paper, we propose a new highly stable soft-error immune SRAM cell with multi-node upset recovery (SIMR-18 T). This design is an improvement from the Quatro-10 T. The design not only tolerates all SEU and performs well in double node upset (DNU). This paper mainly compares with other structures in terms of read and write access time, static noise margin, and critical charge. The write access time of this cell (11.75 ps) is lower than all other cells. The static noise margin for write, about 1010.11 mV, is 151.87% of that of the QUATRO12T. • Compared with other designs, this structure has higher write and hold static noise margin (WSNM and HSNM). • This design not only tolerates all signal event upset (SEU) and performs well in double node upset (DNU). • This structure has a larger critical charge (Q c) of about 90fc. [ABSTRACT FROM AUTHOR]

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell. [ABSTRACT FROM AUTHOR]

Summary: Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. [ABSTRACT FROM AUTHOR]

Radiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge‐boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft‐error‐immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13×/1.38×/0.90×/1.04×/1.03× improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31×/1.17×/1.31×/1.41×/1.01× compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97×/0.98×/1.91×/1.24×/1× when equated to 6T/PP10T/AS8T/Quatro10T/LC10T cell. Improved Inter‐cell and Intra‐cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability. [ABSTRACT FROM AUTHOR]

The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE). Therefore, a 12T SRAM-hardened circuit (RHB-12T cell) for the soft error recovery is proposed using the radiation hardening design (RHBD) concept. To verify the performance of the RHB-12T, the proposed cell is simulated by the 28 nm CMOS process and compared with other hardened cells (Quatro-10T, WE-Quatro-12T, RHM-12T, RHD-12T, and RSP-14T). The simulation results show that the RHB-12T cell can recover not only from single-event upset caused by their sensitive nodes but also from single-event multi-node upset caused by their storage node pairs. The proposed cell exhibits 1.14×/1.23×/1.06× shorter read delay than Quatro-10T/WE-Quatro-12T/RSP-14T and 1.31×/1.11×/1.18×/1.37× shorter write delay than WE-Quatro-12T/RHM-12T/RHD-12T/RSP-14T. It also shows 1.35×/1.11×/1.04× higher read stability than Quatro-10T/RHM-12T/RHD-12T and 1.12×/1.04×/1.09× higher write ability than RHM-12T/RHD-12T/RSP-14T. All these improvements are achieved at the cost of a slightly larger area and power consumption. [ABSTRACT FROM AUTHOR]

Reliability of Static Random Access Memories (SRAMs) is immensely affected by radiation induced soft errors. Multiple Cell Upsets (MCUs) are caused by these soft errors and this lead to data corruption in several SRAM cells. Error Correcting Codes are normally exploited to alleviate the effect of MCUs. Single Error Correction–Double Error Detection (SEC–DED) codes are not the appropriate preference against MCUs rather these codes are suitable for protecting SRAM cells against Single Cell Upset. Single Error Correction–Double Error Detection–Double Adjacent Error Correction (SEC–DED–DAEC) codes are more suitable due to increasing trends of single and double-adjacent errors in SRAM cells. In this paper, a new SEC–DED–DAEC code has been proposed which is proficient of correcting single and double-adjacent errors in SRAMs. Our newly proposed code has been termed as Single and Double-adjacent Error Correcting Code (SDECC). Proposed codecs have been designed by employing new parity check matrices for different word lengths which are frequently applied in memory. The mis-correction probability of proposed SDECC codes are up to 88.24% and 80.67% lesser for 2-random and 3-random bit errors respectively with respect to related existing designs. Proposed codecs have been replicated and synthesized in ASIC environment. It is observed that area and power consumption of the proposed codecs are reduced up to 8.93% and 21.47% compared to the recently published results respectively. [ABSTRACT FROM AUTHOR]

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit. [ABSTRACT FROM AUTHOR]

In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the '0' storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit. [ABSTRACT FROM AUTHOR]

Multiple cell upset (MCU) caused by cosmic radiation is a serious issue related to the reliability of static random access memories (SRAMs) in space application. Due to radiation, single cell or multiple cells of a memory are corrupted. The chances of errors in more than one memory cells are also increasing due to continuous down scaling of technology. Single error, double or triple adjacent errors are most common in this case. Several error correction codes are already introduced for protecting the memories. But many existing error correcting codes have either higher delay and/or power consumption and/or decoder error rate. In this paper, we have introduced 16-bit, 32-bit and 64-bit information length, uniquely decodable single error correction-double adjacent error correction (SEC-DAEC) and single error correction-double adjacent error correction-triple adjacent error correction (SEC-DAEC-TAEC) codes with lower power consumption and delay. In our design, same H -matrix is used for implementing both SEC-DAEC and SEC-DAEC-TAEC codes. Both FPGA and ASIC based synthesis results show that proposed SEC-DAEC and SEC-DAEC-TAEC codes with dimensions (24, 16), (41, 32) and (75, 64) are better compared to existing same dimension codes with respect to area, power and delay. Since, the proposed SEC-DAEC and SEC-DAEC-TAEC codes have low encoder and decoder delay which corresponds to low writing and reading time, consume significantly low power and have zero decoder error rate, so proposed codec can be used for memories in space application. • H -matrices for a new class of fast and power efficient SEC-DAEC and SEC-DAEC-TAEC codes with three different word lengths and 0% decoder error rate have been proposed. • Proposed codes with data length of 16-bit, 32-bit and 64-bit are designed and implemented in FPGA and ASIC platforms. • Performances of proposed codes are evaluated and compared in terms of area, delay and power. [ABSTRACT FROM AUTHOR]

Random Access Memory (RAM) refers to the main memory of a computer. For the central processor unit (CPU) to operate quickly and effectively, it stores operating system software, applications, and other data. Unfortunately, single event upset and other high-soft error problems plague standard static RAM (SRAMs) in aircraft applications (SEU). Many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD), such as the 12T We-Quatro and twelve-transistor (12T) Dice SRAM cells, have been created to address the soft error issues. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 × 32 array architecture. The power consumption of a 32 × 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 × 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology file is used to simulate the comparative analysis for the SRAM cell. [ABSTRACT FROM AUTHOR]

High-energy particles found in space environment can cause single event upsets (SEUs). The severe environments found in space are too harsh for conventional 6T static random-access memory (SRAM) cell as its data get altered when a radiation particle strikes a susceptible place of the cell. Therefore, creating an SRAM that can withstand these demanding space circumstances is essential. This paper proposes a High Speed Radiation Hardened 12T (HSRH12T) SRAM cell which is suitable for low power applications and mitigates the effect of both SEU and multi-bit soft errors. All of the HSRH12T sensitive nodes are capable of recovering their data, even in the event that a radiation impact flips the node values. The HSRH12T demonstrates up to 1.6 × /7.88 × /1.31 × /23.37 × reduction in read delay (T R A), write delay (T W A), leakage and dynamic power consumption, respectively. The proposed cell exhibits up to 1.64 × greater critical charge compared to the other considered cells. [Display omitted] • Its higher critical charge at sensitive nodes ensure strong SEU/SEMNU tolerance. • Utilization of more PMOS transistors reduces sensitive nodes, and SEU impact. • Stacked transistors in the latch core effectively reduce leakage power. • It's dynamic power is less due to the lower bitline capacitance. [ABSTRACT FROM AUTHOR]

Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the failure mechanisms of the FPGA. The SEEs test results for the FPGA device based on the 40 nm CMOS process are significant. [ABSTRACT FROM AUTHOR]

The modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity. [ABSTRACT FROM AUTHOR]

With growing interest in near-threshold voltage regime (NTV) to make energy-efficient circuits, their operation has become less reliable and prone to errors. A soft error is one of the significant reliability concerns in Static random access memories (SRAM) cells, and due to technology scaling, the sensitivity of these SRAM cells to soft errors has increased. The SRAM memories are more susceptible to the radiation effects, mainly Single Event Upsets (SEU). This paper presents a 10T SRAM cell, which gives an energy-efficient operation with high noise margins and is radiation hardened by design. We implement the novel memory cell in an industrial 65-nm CMOS technology and ASAP7 7-nm Fin-FET technology in the NTV regime. The proposed memory cell reduces the area overhead from the QUCCE10T and QUCCE12T cells by 12% and 25% in 65-nm technology. In 65- nm technology, the proposed SRAM cell significantly improves HSNM/RSNM by 24/14% over the recently reported RHPD12T cell with nearly equal WSNM. We also verify the radiation hardness of the proposed memory cell in 32- nm CMOS technology using TCAD simulations. In 32-nm technology, the proposed SRAM cell provides radiation hardness up to the value of LET = 35 MeV cm2/mg. • This paper presents a 10T SRAM cell, which gives an energy-efficient operation with high noise margins and is radiation hardened by design. • The proposed memory cell implement in an industrial 65-nm CMOS technology and ASAP7 7-nm Fin-FET technology in the NTV regime. • The proposed memory cell reduces the area overhead from the QUCCE10T and QUCCE12T cells by 12% and 25% in 65-nm technology. • In 65- nm technology, the proposed SRAM cell significantly improves HSNM/RSNM by 24/14% over the recently reported RHPD12T cell with nearly equal WSNM. • We also verify the radiation hardness of the proposed memory cell in 32- nm CMOS technology using TCAD simulations. In 32-nm technology, the proposed SRAM cell provides radiation hardness up to the value of LET = 35 MeV cm2/mg. [ABSTRACT FROM AUTHOR]

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of $5 \mu \text{m}$ 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain. [ABSTRACT FROM AUTHOR]

This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing '1' issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell. [ABSTRACT FROM AUTHOR]

The shrinking of technology node and supply voltage has a profound effect on various design metrics of the SRAM cell. Available SRAM designs in the literature suffer from half-select issue, increased write delay, leakage power, read power, and lower critical charge. Considering the above concerns, a new P12T SRAM cell was proposed incorporating the cross-point selection to remove half-select issue, adding the inverter between the storage nodes to enhance critical charge, High- V th transistors in read path to reduce the read power and leakage power. The critical charge of P12T SRAM cell is 9.13% and 15.21% higher than the 8T and 10T SRAM cells, respectively, at 0.9 V V DD . P12T SRAM cell has 41.61% and 21.4% decrease in read power than 8T and AS10T SRAM cells, respectively, at SS corner for 0.9 V V DD . In P12T SRAM cell, write 1 PDP at worst case corner SS is 1. 4 × , 2. 9 × , 2. 2 × , 1. 7 × , and 3. 3 × lower than 8T, AS8T, AS10T, 10T, and 12T SRAM cells, respectively, at 0.9 V V DD . Monte Carlo simulation has been done to study variability and half-select issue. 1 Kb bit interleaving SRAM array is designed using P12T SRAM cell and 12T SRAM cell. 1 Kb SRAM array using P12T SRAM cell has superior write PDP than 12T SRAM cell. Postlayout simulation has been carried out on all the SRAM cells to estimate different metrics in 45 nm technology using the Cadence Virtuoso. [ABSTRACT FROM AUTHOR]

Spin orbit torque magnetic tunnel junction (SOT-MTJ) has been widely used for designing nonvolatile flip-flop (NVFF), thanks to its ultrafast switching speed, zero static power consumption, nearly unlimited endurance, etc. However, in the space environment, the write pulse width of the SOT-MTJ is comparable to radiation-induced current duration. Thus, the SOT-MTJ-based NVFF may suffer from soft error induced by the nonvolatile single event upset (NVSEU) in the backup mode. In this paper, we analyze the sensitive nodes in different work modes and propose the radiation hardening circuits for master–slave NVFF (MS-NVFF) to solve the NVSEUs. Based on a physics-based SOT-MTJ compact model and a 40 nm CMOS design kit, the reliability of MS-NVFF is verified by simulation with 2 pC charge, which could be reliably integrated into aerospace and avionics electronics in hostile environments. [ABSTRACT FROM AUTHOR]

The aerospace environment contains extremely energetic particles that trigger single-event transients (SET), leading to single-event upsets (SEU) in the memory cell. An efficient SRAM cell must be designed to tolerate soft error to withstand the extreme environment. This paper proposes a highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. The proposed cell has better writability, and WSNM is 1.08 × higher than its counterpart We-Quatro SRAM cell. The read access time of the proposed SRAM cell is 0.96 × , 0.91 × , 0.99 × , 0.98 × smaller than 6T, Quatro, We-Quatro, and NQuatro SRAM cells, and 1.01 × higher than RHD12T cell, and the write delay of the proposed SRAM is 0.93 × , 0.46 × , 0.72 × , 0.41 × , 0.47 × , less than that of 6T, Quatro, We-Quatro, RHD12T, and NQuatro respectively. 2000 Monte Carlo simulation for power dissipation and upset margin reveals that the process variation has less impact on the proposed SRAM and 1.64 × better tolerance against logic flipping. Further, for the P-Quatro, the critical charge is 41.51 fC and is 2.05 × , 1.75 × , 1.93 × , and 1.48 × greater than Quatro, We-Quatro, RHD12T, and NQuatro memory cells. We conducted an assessment using an electrical quality matrix (EQM) that takes into account all performance parameters. The findings reveal that the EQM of the proposed cell surpasses that of the 6T, Quatro, We-Quatro, RHD12T, and NQuatro SRAM cells by factors of 0.82 × , 0.35 × , 0.49 × , 0.71 × , and 0.21 × , respectively. This indicates that the proposed cell demonstrates superior electrical quality across various metrics compared to the other SRAM cell designs evaluated. • A highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. • Using NMOS transistors instead of PMOS helps reduce charge sharing in the circuit, improving critical charge and reducing soft error upset probability. • The electrical quality matrix (EQM) of the proposed cell surpasses that of the 6T, Quatro, WeQuatro, RHD12T, and NQuatro SRAM cells. [ABSTRACT FROM AUTHOR]

Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level issues is also proposed. Compared with state-of-the-art DNU-resilient latches, simulation results show that the proposed latch exhibits up to 92% delay and 80% power reduction in data activity ratio (DAR) of 100%. The radiation simulation using the dual-double exponential current source model shows that the proposed latch has the strongest radiation-hardening capability among the other DNU-resilient latches. [ABSTRACT FROM AUTHOR]

Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell's stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell's reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions. [ABSTRACT FROM AUTHOR]

Space Electrostatic Discharge Effect (SESD) and Single Event Effect (SEE) are two major space environmental factors that cause spacecraft failure. Previous studies have established that both can lead to soft errors such as upset of memory cells. An ESD generator and a pulsed laser experimental facility were used to test a low-power asynchronous timing monolithic SRAM. The characteristics of soft error number, single/multi-bit upsets, and supply current values were compared for similarities and differences. The test revealed that SEE-induced soft errors were mainly single-bit upsets (SBU), whereas SESD-induced soft errors were predominantly multi-bit upsets (MBU). Additionally, when soft errors occur in the circuits, the current of the power supply drops, which enables the device to be evaluated by monitoring the current value. This study provides experimental support for distinguishing device errors caused by these two effects, as well as references for further accurate identification of in-orbit faults and corresponding protection design. [ABSTRACT FROM AUTHOR]

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply (VDD + = 1. 4 V and VSS − = − 0. 2 V or 200 mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage (VDD = 1. 2 V and VSS = 0 V). A 4 × 4 memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of 4 × 4 array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology. [ABSTRACT FROM AUTHOR]

The reliability of memory is an important issue. The rapid development of transistor technology makes the memory more prone to soft errors. Several recent efforts have proposed various designs to avoid the corruption of stored data by using Error Correction Codes (ECC). However, these designs tend to focus on one indicator, which means they cannot balance the electrical timing, area and power consumption constraints with the increasing of the chip-scale and the operating frequency. In this paper, we propose a design named TECED: A Two-Dimensional Error-Correction Codes Based Energy-Efficiency SRAM Design. We achieve higher energy-efficiency and lower hardware cost by using a two-dimensional error correction codes, and evaluate the design by considering the overall system performance. Comparing with the traditional Hamming code, the evaluation shows that the TECED reduces most of fifty percent of the area overhead and twenty-eight point five percent power consumption of the memory at a specific storage capacity. [ABSTRACT FROM AUTHOR]

Pulsed-laser testing is used to accurately determine single-event latchup (SEL) thresholds for static random-access memories (SRAMs) with different body-tie-to-drain spacings on a mixed-signal application-specific integrated circuit (ASIC), a study that could not be completed using only broad-beam heavy-ion testing. Two distinct approaches were employed with the first approach, an empirical correlation method, exploiting the complementary nature of broad-beam heavy-ion and laser testing. Various single- and dual-port SRAMs exhibited SEL thresholds ranging from 1 MeV-cm2/mg to over 100 MeV-cm2/mg, with a dual-port device possessing the smallest body-tie-to-drain spacing being latchup immune at the highest available test conditions (>300 MeV-cm2/mg). These results have been used to inform a follow-on ASIC design resulting in a significant improvement in chip-level SEL sensitivity. The second approach, a calculational method, uses pulsed-laser measurements and charge-deposition modeling to predict linear energy transfer (LET) thresholds without heavy-ion data. This calculational approach agrees with the empirical approach and therefore shows promise as a predictive tool for SEL threshold estimation, but further validation is required. Overall, these approaches can be effective tools for evaluating SEL susceptibilities and mitigation strategies. [ABSTRACT FROM AUTHOR]

Static random access memories (SRAMs) are prone to a single-event upset (SEU), also known as soft errors, due to transient noise caused by a single strike of radiation. Beam testing has been extensively used to measure the SEU cross section of SRAMs as a function of the linear energy transfer (LET) of charged particle radiation. The evolution of the cross section as a function of LET is called the cross section curve, which plays a vital role in upset rate analysis for hardness assurance. Various analytical models have been developed to describe SRAM SEU cross section curves, and they have proven to be useful in reducing the cost of beam testing as well as revealing the physics behind test results. However, they involve arbitrary parameters, which make it challenging to predict cross section curves without any beam results. Moreover, the current method of analyzing cross section curves or the LET dependence of cross sections relies on a model different from that is used in the analysis of power-supply-voltage dependence, which is becoming increasingly important because of the demand for low-power operation. To overcome these problems, this article proposes a unified equation that describes both LET and the power-supply-voltage dependence of SRAM SEU cross sections. It comprises only parameters that are physically clear and familiar to SEU researchers. As well as giving possible constraints, comparisons with data from the literature suggest it can be applied to SRAMs fabricated in bulk and silicon-on-insulator (SOI) processes across generations from the early 1000-nm-scale to the current 10-nm-scale technology nodes. [ABSTRACT FROM AUTHOR]

With the aggressive growth of the internet of things-based applications in the domestic and industrial domain, the embedded static memory is also under renovation stage to eliminate classical barriers such as soft errors, poor stability, and mediocre performance. In this work, a novel twelve transistors (12T) SRAM cell is presented that replaces the conventional inverter with Schmitt trigger-based inverter in core latch. The proposed SRAM circuit has been compared with four formerly reported designs for investigating the improvement in terms of various performance metrics. These designs include conventional six transistors (6T), tunable transistor 8T (T8T), PPN inverter-based 10T (PP10T), and stable low read power 11T (S11T) cells. The presented cell effectively minimizes the soft errors attributed to 1. 3 6 × / 1. 2 7 × / 1. 6 6 × / 1. 2 7 × enhancement of critical charge compared to 6T/T8T/PP10T/S11T cells. Also, the proposed bit-cell effectively mitigates multi-bit-cell upsets because it allows bit interleaving array structure. The presented bit-cell also shows reduction in leakage power by 1. 0 8 × / 1. 3 3 × / 0. 4 3 × / 1. 2 8 × in comparison to 6T/T8T/PP10T/S11T cells, respectively. The read and write stability of proposed bit-cell circuit is enhanced by 1. 9 6 × / 1. 8 8 × / 1 × / 1. 9 2 × and 1. 1 5 × / 1. 1 9 × / 1. 2 9 × / 1. 4 5 × , respectively, in comparison to 6T/T8T/PP10T/S11T cells, respectively. In addition to this, proposed cell exhibits improvement in dynamic power, data retention voltage, and overall electrical quality matrix. Variability comparison of key design metrics such as read power and read current of the proposed SRAM circuit with 6T cell has also been presented in this work. [ABSTRACT FROM AUTHOR]

Conventional static random‐access memory (SRAM) suffers from high leakage power in advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell embedded dynamic random‐access memory (GC‐eDRAM) is an area‐efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field‐effect transistor (FinFET)‐based 5T GC‐eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth‐consuming refreshes of GC‐eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain‐cell design is based on the FinFET, which overcomes short‐channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all‐nMOS fully depleted‐silicon on insulator (FD‐SOI) gain cell to ensure the static retention of both "1" and "0" data. The 2‐kB array was simulated by employing a 7‐nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all‐nMOS GC‐eDRAM cell in a 28‐nm FD‐SOI technology. [ABSTRACT FROM AUTHOR]

A 256-Mb gate-all-around (GAA) 6T SRAM is implemented in Samsung 3GAE EUV technology. Adaptive dual-bitline (ADBL) and adaptive cell-power (ACP) SRAM assist schemes are proposed to reduce SRAM $V_{\mathrm {MIN}}$. ADBL reduces the effective bitline (BL) resistance up to 62% by connecting auxiliary bitline (AUXBL) of small resistance to BL in the write operation. ACP performs write assist by selecting a farther power switch from the accessed bitcell to improve write margin with the increased cell-power resistance. Silicon shows that both ADBL and ACP improve $V_{\mathrm {MIN}}$ by 230 mV. [ABSTRACT FROM AUTHOR]

On-detector digital electronics in high-energy physics (HEP) experiments is increasingly being implemented by means of static random access memory (SRAM)-based field programmable gate arrays (FPGAs), due to their reconfigurability, fast data processing, and transfer. Radiation-induced single-event upsets (SEUs) in the configuration hinder the correct operation, since they may alter the programmed routing paths and logic functions. In most data acquisition systems, data from clustered front-end modules are aggregated by a single board, which then transmits data to off-detector electronics for acquisition and triggering. In this work, we present a novel scrubber capable of correcting radiation-induced upsets in the configuration of SRAM-based FPGAs by majority voting across clustered modules. We designed it for the Aerogel Ring Imaging CHerenkov (ARICH) counter of the Belle II experiment at the KEK Laboratory, Tsukuba, Japan. We discuss the architecture of the system and its implementation in a Virtex-5 FPGA, in the aggregator board, for correcting the configuration of up to six Spartan-6 LX45 FPGAs, on pertaining front-end modules. We discuss results from neutron irradiation tests at the TRIGA reactor of the Jožef Stefan Institute, Ljubljana, Slovenia, which show that our solution corrects an average of 6.2 k upsets in each target FPGA before the failure of the scrubber. Moreover, with respect to the Xilinx soft error mitigation (SEM) controller, our design improved the mean time before failure of data readout by 30%. [ABSTRACT FROM AUTHOR]

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU's chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM) [1–3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs. • This work exploits the latest advances in Gain-Cell technology and analyzes its potentials in low Power On-Chip memory implementation. • To our knowledge, this is the first proposal of SRAM and Gain-Cell eDRAM hybrid architecture in first level data (L1D) cache and L2 cache (SRAM tag array and GC-eDRAM data array). • We analyze tradeoffs in performance, area and power of our proposed hybrid architecture in comparison to conventional SRAM baseline. [ABSTRACT FROM AUTHOR]

Advent and rapid development of on-chip computation in applications based on internet of things has opened space for integration of human life processes with technology. Wireless sensor node is a crucial component of this integration and SRAM employed in these nodes is under renovation phase. In this work, a novel single ended, bit-line powered 10T static random-access memory cell is proposed which improves access time, dissipates low power and supports bit-interleaving. The performance metrics of proposed design are compared with conventional 6T (conv.6T), tunable 8T(TUA8T), transmission gate based 9T(TRD9T), PPN10T(P10T), Schmitt-trigger based 10T (STR10T), loop cutting 10T (LC10T), and data dependent 11T(DD11T) cell to affirm the novelty of observed results. The reduction of soft error in proposed 10T cell is indicated by 1.22 × /1.13 × /1.13 × /0.91 × /1.49 × /1.12 × improvement in critical charge in comparison to conv.6T/TUA8T/TRD9T/STR10T/P10T/LC10T cell respectively. The read and write delay of proposed cell is improved by 1.56 × /1.04 × //1.04 × /1.57 × /1.14 × /1.12 × /1.05 × and 3.29 × /2.29 × /2.49 × /7.94 × /7.15 × /3.38 × /2.32 × respectively compared to conv.6T/TUA8T/TRD9T/STR10T/P10T/DD11T/LC10T cell. Additionally, read and write static noise margin of proposed 10T cell is improved by 2.22 × /2.04 × /1 × /1.67 × /1.06 × /1.75 × /1 × and 1.18 × /1.22 × /0.89 × /0.93 × /1.23 × /1.33 × /0.98 × respectively in comparison to conv. 6T/TUA8T/TRD9T/STR10T/P10T/DD11T/ LC10T cell. This article further demonstrates 1.88 × and 1.26 × tighter disperse in read power variability and read current variability respectively as compared with that of conv. 6T SRAM cell. The reduced cell density due to more number of transistors is compensated by improved I on / I off ratio. [ABSTRACT FROM AUTHOR]

Satellite communication plays a vital role in extending 5G cellular networks to hard-to-reach areas, including airplanes, railways, shipments, other transport mechanisms, and especially in rural regions of the country that are traditionally beyond the reach of cellular service providers. The devices, specifically those incorporating static memories, being employed for satellite communication, face the challenge of getting prone to cosmic radiations or alpha particle strikes. These strikes cause multi-bit errors in static-memory cells that lead to loss of total output yield. This work proposes a low power twelve transistor (12T) SRAM cell that confirms a reduction in multi-bit errors for the Internet of things based devices supporting fifth-generation (5G) communication system. The proposed SRAM ensures improved read and write ability by utilizing a read decoupled access path and loop cutting mechanism, respectively. The proposed design improves read/write stability by 2.02 × /1.05 × in comparison to conventional 6T cell with 2.52 × silicon space overhead. The area overhead is neutralized by 3.17 × improvement in I on / I off ratio that improves cell density of SRAM cell. The improved critical charge of the proposed 12T SRAM cell is compared with four other considered cells to ensure the reduction in multi-bit soft errors, and thereby confirming its suitability for devices supporting satellite communications. The proposed design successfully eliminates the half-select issue that enables the implementation of the bit-interleaved architecture. The leakage power of the proposed 12T cell is improved by 2.65 × in comparison to conventional 6T attributed to series-connected devices used as loop cutting pair. This reduction of leakage power remains sustained till 110 ∘ temperature. The simulation of this work has been conducted with cadence virtuoso tool using GPDK 45 nm technology file. [ABSTRACT FROM AUTHOR]

Convolutional neural networks (CNNs) are widely adopted in safety-critical systems, including space applications and autonomous vehicles. Field-programmable gate arrays (FPGAs) based on SRAM are preferred for accelerating CNN computations due to their unique characteristics. However, the configuration memory of FPGAs is susceptible to single event effects (SEEs), which can corrupt computations and lead to misclassification of CNN outputs. In this study, we investigated the impact of SEEs on SRAM-based FPGAs with Two-Photon Absorption (TPA) laser fault injections through a comparative analysis of two popular CNN acceleration architectures: streaming architecture (SA) and single compute engine (SCE). Experimental results show that SA-based CNNs require more hardware resources but exhibit superior resilience against single event upsets (SEUs). Without any Radiation Hardened by Design (RHBD) protection, SCE has an error rate approximately twice as high as SA. To mitigate errors, the Xilinx IP core - Soft Error Mitigation (SEM) is used for error detection and correction, leading to error rate reductions of up to 50 % in both architectures. Importantly, we propose the AutoDPR-SEM (Autonomous Dynamic Partial Reconfiguration for Soft Error Mitigation) approach, which automatically reconfigures the SEM IP core when it remains idle due to uncorrectable errors. AutoDPR-SEM significantly improves CNN error rates, reducing errors by approximately 17.8 times in SCE and 14.8 times in SA. We also applied software level simulation to validate the TPA experiment, showing similar trends of the testing results across all models. In conclusion, the study confirms the feasibility of AutoDPR-SEM in both architectures, showcasing its potential to improve CNN error rates in safety-critical systems. • Implemented two FPGA-based CNN accelerator architectures: Streaming and Single Computation Engine. • Conducted sensitivity evaluations of the FPGA-based CNN accelerators using laser injection. It has been validated through software simulations. • Improved reliability of these two architectures by implementing the underlying Soft Error Mitigation (SEM) IP core. • Developed dynamic partial reconfiguration (DPR) technology to improve SEM capabilities without introducing redundancy in timing. • Validated radiation hardening using laser test and software simulation; identified SEM core with DPR is effective. [ABSTRACT FROM AUTHOR]

B Abstract b Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. In the year 2004 she received her M.Sc. Degree in Electrical Engineering at Pontifical Catholic University of Rio Grande do Sul (Brazil) and in 2008 her Ph.D. in Computer Engineering from the Politecnico di Torino (Italy). Graph B Tiago Roberto Balen b received the Electrical Engineering degree, MSc and PhD degrees from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 2004, 2006, and 2010, respectively. [Extracted from the article]