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This paper introduces the concept of time-based sensing (TBS) for bitcell read in spin transfer torque magnetic RAMs arrays. The TBS scheme converts the bitline voltage into time, then the sense amplifier discriminates the two bitcell levels in the time domain. The TBS scheme substantially improves the read yield compared to conventional voltage sensing (CVS). As further advantage, TBS requires no analog reference generation and distribution by leveraging the implicit timing reference set by the gate delay in the sense amplifier. Monte Carlo simulations in 65 nm show that the proposed TBS improves the read bit error rate (BER) by two-three orders of magnitude, compared to CVS. This is achieved at the cost of less than 1% area penalty and 13–14% performance degradation, and insignificant (2%) energy penalty when designed at iso-area (minimum delay). Compared to other sensing schemes at iso-BER, the proposed TBS scheme achieves a more favorable area-robustness-energy-performance tradeoff. [ABSTRACT FROM AUTHOR]

This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR). Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming to widen the difference between the bitline and the reference voltage (i.e., the read margin). As a result, larger variations can be accommodated, thus improving the read robustness and substantially reducing the read failure rate. This DR scheme does not require any change in the bitcell and requires minimal modifications of conventional arrays, hence it can be jointly used with existing assist techniques enhancing the read robustness. From Monte Carlo simulations in 65 nm, the proposed DR scheme improves the read bit error rate by two orders of magnitude across a wide range of voltages (0.75–1.2 V) compared with the conventional voltage sensing scheme. This is achieved at 0.3% area overhead, less than 15% performance degradation, and less than 25% energy penalty. Furthermore, the joint adoption of the DR approach and switched-cap bitline boosting further reduces the sense amplifier area by 25% at iso-failure rate, and reduces the energy by 6–10% compared with the standalone DR. [ABSTRACT FROM AUTHOR]

This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages. The BVS scheme mitigates the impact of variations in the senseamp and the reference voltage generation, and is based on switched-capacitor voltage boosters. The related area-performance-energy-resiliency tradeoff is explored, and design guidelines are derived to improve the read margin at minimum overhead. [ABSTRACT FROM PUBLISHER]