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In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (${L}_{g}$) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance. [ABSTRACT FROM AUTHOR]

In this letter, the dynamic Ron degradation mechanisms of the p-GaN gate HEMTs induced by off-state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including VTH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The VTH positive shift diminishes the drain current by shrinking the overdrive VGS, which however, can be compensated by a higher VGS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and VTH shift have a very slow recovery process. [ABSTRACT FROM AUTHOR]

We report measurements of multiple hot-carrier (HC) stress and high-temperature anneal cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS technology. We model this cycled HC degradation anneal assuming Si–H bond breakage during stress and bond passivation during anneal, with the bond dissociation and passivation energies following a bivariate Gaussian distribution. Our model can describe multiple stress and anneal time scenarios well using a single parameter set and provides insights into the recovery behavior of HC-induced defects. We find no correlation between bond dissociation and passivation energies and observe that the repeated HC stress and anneal cycles suppress the low energies from the distribution of bond passivation energies, changing its shape from the Gaussian to a non-Gaussian form. [ABSTRACT FROM AUTHOR]

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias (VBG) is applied only during ON-state and a constant front-gate stress VG is used, BTI reliability is not influenced by the applied VBG (due to its negligible impact on the front-gate oxide field, Eox). Therefore, supplying an FBB during ON-state can be used to adjust device performance—as VBG modulates the channel current through Vth and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress Vov is maintained by adjusting the front-gate VG [i.e., VG – Vth (VBG) is kept constant under different VBG’s], the BTI reliability can be improved under FBB (due to a reduced Eox in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation. [ABSTRACT FROM AUTHOR]

Operating temperature has a significant imp-act on the reliability of metal–oxide–semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ($\Delta {N}_{\text {eff}}$) at operating condition typically shows an Arrhenius temperature dependence with ${E}_{\text {A}}$ ~ 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77–373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture–emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total $\Delta {V}_{\text {th}}$ measured in bias-temperature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. [ABSTRACT FROM AUTHOR]

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process. [ABSTRACT FROM PUBLISHER]

To predict the negative bias temperature instability (NBTI) toward the end of pMOSFETs’ ten years lifetime, power-law-based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to ten years. The objective of this paper is to find how to make n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps, a new method is proposed to capture the generated defects (GDs) in their entirety. n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under ac operation, the model predicts that the GD can contribute to ~90% of NBTI at ten years. [ABSTRACT FROM PUBLISHER]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse- \(I\) – \(V\) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias. [ABSTRACT FROM PUBLISHER]

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 ^\circC ; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev , when neutral, lift well above Ev after charging, and return below Ev following neutralization. [ABSTRACT FROM PUBLISHER]

Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with \N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high-k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG \sim VD/\2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis. [ABSTRACT FROM PUBLISHER]

A methodology for the design of circuits robust to system-level electrostatic discharge (ESD) stress is presented and verified with two case studies. The combination of on-wafer characterization and transient simulations enables the ESD designer to study the behavior of the component-level ESD protection design during system-level ESD stress with and without adding off-chip protection devices. The design of a system-level ESD protection solution can be verified long before IC packaging and even before the final system is built. [ABSTRACT FROM PUBLISHER]

This paper presents an extensive statistical study on the impact of bias temperature instability (BTI) on digital circuits. A statistical framework for the evaluation of BTI at the electrical (SPICE) level, enhanced by an atomistic model for BTI, is introduced. This framework is then employed to perform the timing analysis of different combinational paths using cells from a given library, aiming to statistically model BTI at the higher abstraction level. A statistical static timing analysis (SSTA) method is then performed and the results are compared to detailed simulations using atomistic models based on experimental data. The comparison between the two methods shows that for large paths both methods converge to the same distribution for the delay while for short paths the delay distributions are different causing the SSTA method to generate misleading results. An analysis is then performed in order to understand and formalize the results. [ABSTRACT FROM AUTHOR]

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a \SiO2/ \HfO2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups. [ABSTRACT FROM PUBLISHER]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG\sim VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism. [ABSTRACT FROM PUBLISHER]

Variability of nanometer-size devices is a major challenge for circuit design. Apart from the as-fabricated variability, the postfabrication degradation introduces a time-dependent variability, originating from statistical distribution of charge location and number. The existing characterization techniques do not always capture the maximum degradation. Some of them does not separate the device-to-device variation from the charging fluctuation within the same device, either. The objective of this paper is to develop a new analysis method for characterizing time-dependent device-to-device variation, accounting for within-device fluctuation (TVF). The TVF captures the maximum degradation, separate device-to-device variation from within-device fluctuation, and reduce the data points by three orders of magnitude. It is shown that the popular data acquisition at discrete time points does not capture the fluctuation well and drain current must be measured continuously. The TVF shows that degradation has two components—a fluctuation with time and one whose discharge is not observed under a given bias. Although both of them increase with stress time, the correlation between them is weak, indicating two different origins. [ABSTRACT FROM AUTHOR]

Three system-level electrostatic discharge (ESD) design methodologies are compared using an RF buffer amplifier as case study. First, the system-level ESD protection is designed with datasheet information. The obtained overdesigned ESD protection is optimized with the System-Efficient ESD Design (SEED) methodology. The SEED-based protection design is further optimized using human metal model testing and transient simulations. The final ESD protection design requires five times less area on the application board, and the capacitive loading is six times lower than when designing with datasheet information. [ABSTRACT FROM PUBLISHER]

The time-dependent variability of nanoscaled \Si0.45 \Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as \1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology. [ABSTRACT FROM AUTHOR]

We report extensive experimental results of the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The results clearly show that this high-mobility channel technology offers significantly improved NBTI robustness compared with Si-channel devices, which can solve the reliability issue for sub-1-nm equivalent-oxide-thickness devices. A physical model is proposed to explain the intrinsically superior NBTI robustness. [ABSTRACT FROM AUTHOR]

Defects in gate oxide cause breakdown and shorten device lifetime. Early works mainly focused on generation process that converts a precursor into a charged defect. Although it can be neutralized through “recovery,” the defect is still there and will recharge when resuming stress. Recently, we have shown that this is not always the case and some defects can be lost, but a detailed investigation is missing. The central objective of this work is to accurately define and extract the loss, separate it from slowdown, and evaluate their enhancement of device lifetime. Loss is defined as elimination of defects, while slowdown means that recharging a “hardened” precursor takes longer than charging a fresh one. Clear evidences show that losses originate from permanent components, i.e., generated interface states and antineutralization positive charges, while slowdown occurs to both permanent and recoverable components. Loss is thermally accelerated, but slowdown of recoverable component is not. This improved understanding adds slowdown and losses to the existing framework for defects. For the first time, we report that the losses and slowdown enhance device lifetime by a factor of 2.6–4.3, for an allowed threshold voltage shift of 20–45 mV. [ABSTRACT FROM AUTHOR]

The ESD robustness of GaN-on-Si Schottky diodes is investigated using on-wafer HBM and TLP. Both forward and reverse diode operation modes are analyzed as a function of device geometry, which strongly impact the corresponding failure mechanism. In forward mode, the anode-to-cathode length reduction and the total device width increase are beneficial for ESD robustness; however, in reverse mode, the ESD robustness does not depend on the total device width and saturates at around 400 V for medium and long anode-to-cathode lengths. The corresponding failure mechanisms are respectively attributed to the current distribution and Si substrate breakdown under forward and reverse mode ESD stresses. [ABSTRACT FROM PUBLISHER]

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of \Si/SiO2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI. [ABSTRACT FROM AUTHOR]

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition \HfO2 high-\kappa and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around \10^-8\ \cm^2, implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents. [ABSTRACT FROM PUBLISHER]

A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example. [ABSTRACT FROM PUBLISHER]

Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8- \\rm\AA EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-\\rm \AA EOT device. Clear charge pumping currents are obtained on the 5.8- \\rm\AA EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-\\rm\AA EOT device is found to be higher than that in the 10.1- \\rm\AA EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2 \\rm\AA inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8- \\rm\AA EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1- \\rm\AA EOT device. The bulk trap Not generated after stress is higher in the 5.8- \\rm\AA EOT device due to the higher initial bulk trap density. [ABSTRACT FROM AUTHOR]

The off-state degradation of n-channel laterally diffused metal–oxide–semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an \n^+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both off-state and ESD reliability. [ABSTRACT FROM AUTHOR]

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 \mu\s, which would be missed if the CCP were used. [ABSTRACT FROM PUBLISHER]

In ultrascaled complimentary metal–oxide–semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (\SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal–oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or \SiO2 as a dielectric. [ABSTRACT FROM PUBLISHER]

Based on the so-called defect-centric statistics, we propose the average impact of a single charged trap on FET threshold voltage as a physically based measure of the random component of time-dependent variability. We show that it can be extracted using matched pairs, analogously to time-zero variability. To that end, the defect-centric statistics of matched pairs are discussed and the correlation between time-zero and time-dependent variances is formalized. [ABSTRACT FROM AUTHOR]

CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer (or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress. [ABSTRACT FROM PUBLISHER]

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3/GeO2/Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise. [ABSTRACT FROM PUBLISHER]

GaAs high-electron-mobility transistors (HEMTs) have been widely used for radio-frequency (RF) applications due to the excellent material properties. One of the essential elements of the HEMTs is the gate Schottky barrier layer. InGaP has been proposed and proven as a better Schottky barrier material for the RF performance of the GaAs HEMTs. This letter investigates the influence of the GaAs HEMTs with two different Schottky layers, which are InGaP and AlGaAs on device transient characteristics under electrostatic discharge (ESD) stress. Although InGaP presents significant advantages on improving RF performance of GaAs HEMTs, it shows inferiority in ESD robustness. [ABSTRACT FROM AUTHOR]