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This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is 235.23×301.67 μm2. [ABSTRACT FROM AUTHOR]

The paper demonstrates an efficient process flow for the Hardware Testing of an ASIC (Application Specific Integrated Circuit). The procedure is implied on Comparator, ADC (Analog-to-Digital) and Present Cipher Crypto ASIC. This involves the testing functionality of an Analog, Digital and Mixed Signal design ASIC. The results obtained during functional testing are verified through simulations on Cadence, in case of comparator and ADC ASIC, and vivado in case of Crypto ASIC. The method gives high accuracy and requires less power even at high frequency. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

A voltage supply scalable analog voltage comparator for a wide input range is presented in this paper. A digital gate-based methodology is used to design the comparator in order to extend the use of automation in the analog designs. Therefore, the proposed comparator is enormously cost-effective, reduces the time-to-market, scalable to newer technologies, and more immune to process variations than the conventional CMOS analog voltage comparators. The comparator is designed using Semi-Conductor Laboratory (SCL) 180 nm digital CMOS technology at a supply voltage of 1.8 V. The power consumption of the proposed comparator is 160 µW approximately with total delay and offset voltage of 1.63 ns and 4.28 mV, respectively. Also, 4-bit and 5-bit flash ADC is designed as an application. The measured values of DNL/INL are ± 0.4/± 0.4 LSB and 0.42/± 0.6 LSB for 4-bit and 5-bit, respectively. [ABSTRACT FROM AUTHOR]

This paper presents variable resolution SAR ADC with digitally implemented Bit enhancement logic. Unlike conventional approaches, this work avoids complex hardware architecture to reduce power consumption as the variable resolution is achieved using digitally implemented VRL (Variable Resolution Logic) block instead of combining different ADC configurations altogether. The proposed architecture utilizes the VRL block to enhance the resolution. This work first uses the linear range of an 8-bit SAR ADC as a learning dataset and then uses corresponding output bits as training data for VRL block. This VRL block further enhances the resolution with the help of a 2-bit voltage-to-digital converter by self-adjusting the required resolution after estimating the error. Less variation in sampling rate from 250 MHz to 175 MHz is achieved after implementing the VRL block. The proposed architecture is designed in 180 nm CMOS technology to validate the work. The simulation results show the ADC achieves an SNDR of 47.4 dB for 8-bit and increases to 72.11 dB for 12-bit resolution. The FoM of 253 fJ/conversion step for 8-bit SAR ADC is achieved, and it ranges from 168.3 to 35.7 fJ/conversion step in Variable resolution block phase. The area of the proposed ADC is 315.86 × 151.30 µm2. [ABSTRACT FROM AUTHOR]

A high-resolution dynamic voltage comparator with an input signal dependent power down technique for low power applications is presented here. Without affecting the resolution, a preamplifier stage has been removed from the proposed dynamic voltage comparator in order to reduce the power consumption and its delay. In this design, an input signal dependent power-down technique is used. The proposed design consists of NMOS & PMOS Input Stage Dynamic Voltage Comparator with power down (NISDVC_PD & PISDVC_PD) along with multiplexers for full rail-to-rail input swing. One out of PISDVC_PD and NISDVC_PD is active at a time to reduce power consumption. The proposed comparator has been designed using SCL 180 nm CMOS technology at 1.8 V. The simulation results of the proposed design show that the power consumption and delay is 94.1 µW and 208.28 ps at 500 MHz whereas at 2 GHz the value of the power consumption and delay is 147.7 µW and 212.5 ps, respectively. Furthermore, the offset voltage is obtained as 185.3 µV and the sensitivity of the circuit is 0.15 µV. [ABSTRACT FROM AUTHOR]