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The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. This includes a wide range of applications, such as in-memory computing or memristive logic. A major advantage of the considered HfO $_{2}$ -based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem is that their fabrication still leads to device variabilities, which makes it challenging to test their functionality in an experimental fashion. This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. We aim to provide an enhanced model for multilevel capable RRAM devices, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE or VERILOG-A. Furthermore, we provide an algorithmic model, based on the wave digital (WD) concept, which allows for emulating the considered devices in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements. Finally, we extend the WD model to describe an array composed of RRAM devices for performing vector-matrix multiplication. [ABSTRACT FROM AUTHOR]

Resistive cross-point memory arrays can be used to construct high-density storage-class memory. However, coupled IR drop and sneak currents cause multidimensional non-uniformity of cell effective voltage in cross-point arrays. The voltage non-uniformity significantly degrades write performance on cross-point memory if only adopting the worst-case write latency at partial dimensions. Furthermore, the non-uniformity of cell effective voltage in cross-point arrays depends on multidimensional dynamic write operation parameters: row, column as well as layer address, the number of selected cells, and the number of half-selected low-resistance state cells. In this article, we aim to improve the write performance by leveraging multidimensional non-uniformity of cell effective voltage. First, we analyze the impact of multidimensional write parameters on effective voltage and write latency. Then, we design the memory array write scheme that measures the write parameters and sets the write latency accordingly. We further analyze the features and effects of interlayer sneak currents and extend the scheme to 3D cross-point memory. The evaluation shows that the proposed memory array write scheme can reduce the memory access latency by 75.6 and 64.1 percent, and improve the system performance by 4.5 times and 3.4 times on average, compared with the baseline and the state-of-the-art approach, respectively. [ABSTRACT FROM AUTHOR]

Resistive memory is promising to be constructed as a high-density storage-class memory. Multilevel cell, access-transistor-free cross-point array structure, and 3-D array integration are three approaches to scale up the density of resistive memory. However, composing the three approaches together strengthens the interactions between array-level and cell-level nonidealities (interconnect resistance-induced IR drop, sneak current, and device variability) of resistive memory arrays during write operations and significantly degrades write performance and reliability. In this article, we analyze the dynamic voltage-dividing effect along a selected write current path in 3-D cross-point memory arrays. We propose a nonideality-tolerant high-density resistive memory (HD-RRAM) architecture, that can weaken the interactions between nonidealities and mitigate their degradation effects on the performance and reliability of array multilevel write operations. HD-RRAM is equipped with a double-transistor array architecture with two-transistor-n-resistor (2TnR) cell organization along pillars to reduce the current driving requirement and the large undesired voltage drop across each vertical pillar access transistor. Moreover, multiside asymmetric bias improves the resistive switching velocity by leveraging current-dividing effects. Variability-aware multilevel state partition reduces the worst-case write error rate by leveraging target state dependency of variability. Proportional-control multilevel state tuning reduces the average number of required write-and-verify iterations by leveraging pulse amplitude dependency of variability. Multilevel cell parallel writing improves the cell-level parallelism by leveraging the pass-through feature of intermediate resistance states. The evaluations show that HD-RRAM reduces both memory access latency and energy consumption over an aggressive baseline. [ABSTRACT FROM AUTHOR]

The deployment of IoT has brought on the generation of massive amounts of data in need of analysis. In recent times, resistive switching-based crossbar arrays have been presented as a viable candidate for the acceleration of neural network inference, in pushing beyond the limit of CMOS process scaling so as to keep pace with the ever-growing complexity of computation. While plenty of empirical and physically descriptive models exist, their simulation run times become inconvenient for users when used in large scale crossbar arrays. In this brief, we first present a behavioral model of digital resistive switching devices, demonstrated on experimental PCM data to exhibit generality which can see useful implementation in circuit analysis methods for compute-in-memory applications. This model is based on a pair of nonlinear ordinary differential equations that request switching time and threshold voltage inputs from the user, which are the most important concerns for binarized weights in crossbar arrays. By stripping the model of detailed physical characteristics that is not required at the systems level, we demonstrate an improvement of computational run time of up to 20-fold over state-of-the-art physics-based models, and 1.3 times over the most commonly used empirically driven models. [ABSTRACT FROM AUTHOR]

The parallelism and analog computing features of neuromorphic systems bring great challenges in developing a compact model of analog resistive random access memory (RRAM). In this article, we develop a physics-based compact model for analog RRAM devices and crossbar array. Nonideal effects of analog RRAM device, such as variability, I – V nonlinearity, programming nonlinearity and asymmetry, and tuning voltage sensitivity, are modeled and verified with the statistical data measured from RRAM array. Modeling of parallel-vector-matrix-multiplication and weight update process on RRAM crossbars with interconnect resistance enables fast and accurate estimation of the training accuracy. Benchmarks of neural networks under different hardware conditions validate the functionality of the proposed model. This model can provide valuable design guidelines for a practical neuromorphic system with high performance and computing accuracy. [ABSTRACT FROM AUTHOR]

Multilevel cell cross-point memory arrays can be used to architect high-density resistive memory. However, coupled sneak current and IR drop cause cell-to-cell nonuniformity of multilevel readout current in cross-point memory arrays during read operations. To eliminate sneak currents along the selected bit-lines (BLs) and regulate sneak currents along the selected word-line (WL), we design unselected WL grounding, unselected BL partial-biasing parallel read scheme. Then, we analyze the impact of the partial-bias coefficient on effective read voltage and array power consumption. We observe that multilevel readout currents are only sensitive to BL location. Therefore, to improve the array-level multilevel read margins, we further propose a BL location-adaptive multilevel read reference setting scheme that groups adjacent BLs and shares the multilevel references in a fine-grained fashion. We also analyze the impact of reference sharing granularity, IR drop coefficient, resistance ratio, and the number of resistance states per cell on the array-level multilevel read margins. SPICE simulation shows that sharing multilevel read references across the entire cross-point array with the size of 512 × 512 can only distinguish 12 resistance states, whereas our design can distinguish all the 16 resistance states throughout the array and can improve the normalized array-level read margin from −1.04 to 0.23. [ABSTRACT FROM AUTHOR]

Modern GPUs feature an increasing number of streaming multiprocessors (SMs) to boost system throughput. How to construct an efficient and scalable network-on-chip (NoC) for future high-performance GPUs is particularly critical. Although a mesh network is a widely used NoC topology in manycore CPUs for scalability and simplicity reasons, it is ill-suited to GPUs because of the many-to-few-to-many traffic pattern observed in GPU-compute workloads. Although a crossbar NoC is a natural fit, it does not scale to large SM counts while operating at high frequency. In this paper, we propose the converge-diverge crossbar (CD-Xbar) network with round-robin routing and topology-aware concurrent thread array (CTA) scheduling. CD-Xbar consists of two types of crossbars, a local crossbar and a global crossbar. A local crossbar converges input ports from the SMs into so-called converged ports; the global crossbar diverges these converged ports to the last-level cache (LLC) slices and memory controllers. CD-Xbar provides routing path diversity through the converged ports. Round-robin routing and topology-aware CTA scheduling balance network traffic among the converged ports within a local crossbar and across crossbars, respectively. Compared to a mesh with the same bisection bandwidth, CD-Xbar reduces NoC active silicon area and power consumption by 52.5 and 48.5 percent, respectively, while at the same time improving performance by 13.9 percent on average. CD-Xbar performs within 2.9 percent of an idealized fully-connected crossbar. We further demonstrate CD-Xbar's scalability, flexibility and improved performance per Watt (by 17.1 percent) over state-of-the-art GPU NoCs which are highly customized and non-scalable. [ABSTRACT FROM AUTHOR]

Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data that can be used for integrity checking. An analytical approach to model such a tag generation process is described in this paper. Security results predicted by the analytical model provide various design options leading to an optimal system from the perspective of considered security properties. The proposed design is simulated to investigate and verify the security properties of the system for a number of optimal design options predicted by the analytical model. Reliability of the proposed system is also measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage. Finally, the performance of the proposed system is compared against another existing lightweight tag generation method from the perspective of energy consumption, transistor count, and delay. [ABSTRACT FROM AUTHOR]

Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic, and in-memory computing applications. This paper presents a 2M1M crossbar architecture, capable of memory and logic applications, based on a transistor-less memory cell, which behaves as a switching circuit. The proposed memory cell consists of two access and one target memristors that utilize a gating structure by access devices to reduce sneak path effect. This paper has considerably lower wiring density and lower number of memristors per bit compared with its peers. Therefore, it can be a suitable structure for high-density memory and logic applications. In addition to its in-memory computing capabilities, 2M1M structure as a memory offers higher density and less energy consumption in comparison with conventional CMOS-based static random access memory. In comparison with previous works, simulation results show significant improvements in basic implementation costs of the memory cell in terms of write time (1.11 ns), read time (200 ps), density (80 Gb/cm2), energy consumption ($23.2\times 10^{-3}\,\,\mathrm {fJ/bit}$), and wiring complexity. Also, it has a sneak path current of 90-nA per memory cell operation which is considerably lower compared with its peers. [ABSTRACT FROM AUTHOR]

Resistive random-access memory (RRAM) technology has been gaining importance due to scalability, low power, non-volatility, and the ability to perform in-memory computing. The RRAM sensing applications have also emerged to enable single RRAM technology platforms which include sensing, data storage, and computing. This paper reports on sol-gel drop coated low-power $\mu $ -thick Ag/TiO2/Cu memristor, named MemSens, developed for radiation sensing. MemSens exhibits a bipolar memristive switching behavior within a small voltage window, ranging up to +0.7 V for the turn-ON, and down to −0.2 V for the turn-OFF. Under these operating conditions, MemSens has 67% less switching voltage, 20% drop in ON switching current, 75% reduced active area and > 3x improved device endurance, compared to the best characteristics reported in the literature for $\mu $ -thick memristors. The device is tested under direct exposure to ionizing Cs-137 662keV $\gamma $ -rays, during which a significant increase in the electrical conductivity of the device is observed. MemSens circuit is proposed to allow a relatively real time and cost-effective radiation detection. This provides a first insight to the advancement of reliable memristors that could potentially be deployed in future low-power radiation sensing technologies for medical, personal protection, and other field applications. [ABSTRACT FROM PUBLISHER]

The packing density associated with crossbar arrays offers important architectural solutions to numerous forms of computational engines. Mitigation of sneak paths in the crossbar array, however, requires additional layers in fabrication technology to impede current flow in order to avoid undesired changes to the state when reading and writing to and from the array. This results in an unavoidable increase in the vertical stacking dimension of the array. With the recent emergence of bistable memristors under both dc and ac, by adopting their asymptotic dynamics, we realize a significant improvement in memory construct and spatial constraints of memristor crossbar arrays. In this brief, we formalize a method of configuring a whole array architecture to any permutation of states without sacrificing array density by using a rigorous theoretical analysis, and confirmed via simulation. [ABSTRACT FROM AUTHOR]

The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power. [ABSTRACT FROM PUBLISHER]

In this paper, the susceptibility of oxide-based resistive switching random memory (RRAM) to heavy ion strikes is investigated. A physics-based SPICE model calibrated with \HfOx RRAM is employed for circuit and array-level simulations. The RRAM state-flipping is attributed to the transient photocurrents at neighboring transistors. Single-bit-upset (SBU) caused by either single-event upset (SEU) or multiple-event upset (MEU) is modeled and simulated in the one-transistor and one-resistor (1T1R) array, which corroborates with experimental observations. In addition, circuit simulation is performed to investigate the impact of transient-induced soft errors in a 1024 \times 1024 crossbar array. The sensitive locations in crossbar arrays are the driver circuits at the edge of the array. The simulations show that the crossbar array with \HfOx RRAM is of high radiation tolerance thanks to the V/2 bias scheme. However, multiple-bit upset (MBU) may occur if using other oxide materials with lower operation voltage. Voltage spikes generated at the edge of the array may propagate along rows or columns as there is no isolation between cells in the crossbar array. [ABSTRACT FROM AUTHOR]

Devices that exhibit resistive switching are promising components for future nanoelectronics with applications ranging from emerging memory to neuromorphic computing and biosensors. In this brief, we present an algorithm for identifying switchable devices, i.e., devices that can be programmed in distinct resistive states and that change their state predictably and repeatedly in response to input stimuli. The method is based on extrapolating the statistical significance of difference in between two distinct resistive states as measured from devices subjected to standardized bias protocols. The test routine is applied on distinct elements of 32 $\times$32 resistive-random-access-memory (RRAM) crossbar arrays and yields a measure of device switchability in the form of a statistical significance $p$-value. Ranking devices by $p$-value shows that switchable devices are typically found in the bottom 10% and are therefore easily distinguishable from nonfunctional devices. Implementation of this algorithm dramatically cuts RRAM testing time by granting fast access to the best devices in each array, as well as yield metrics. [ABSTRACT FROM PUBLISHER]

A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage delivery, current delivery, and power consumption. Two different write schemes, V/2 and V/3, were considered, and the V/2 write scheme is preferred due to much lower power consumption. A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation. [ABSTRACT FROM AUTHOR]

Passive crossbar resistive random access memory (RRAM) arrays require select devices with nonlinear I-V characteristics to address the sneak-path problem. Here, we present a systematical analysis to evaluate the performance requirements of select devices during the read operation of RRAM arrays for the proposed one-selector-one-resistor (1S1R) configuration with serially connected selector/storage element. We found high selector current density is critical and the selector nonlinearity (ON/OFF) requirement can be relaxed at present. Different read schemes were analyzed to achieve high read margin and low power consumption. Design optimizations of the sense resistance and the storage elements are also discussed. [ABSTRACT FROM PUBLISHER]

Large systems-on-chip (SoCs) and chip multiprocessors (CMPs), incorporating tens to hundreds of cores, create a significant integration challenge. Interconnecting a huge amount of architectural modules in an efficient manner, calls for scalable solutions that would offer both high throughput and low-latency communication. The switches are the basic building blocks of such interconnection networks and their design critically affects the performance of the whole system. So far, innovation in switch design relied mostly to architecture-level solutions that took for granted the characteristics of the main building blocks of the switch, such as the buffers, the routing logic, the arbiters, the crossbar's multiplexers, and without any further modifications, tried to reorganize them in a more efficient way. Although such pure high-level design has produced highly efficient switches, the question of how much better the switch would be if better building blocks were available remains to be investigated. In this paper, we try to partially answer this question by explicitly targeting the design from scratch of new soft macros that can handle concurrently arbitration and multiplexing and can be parameterized with the number of inputs, the data width, and the priority selection policy. With the proposed macros, switch allocation, which employs either standard round robin or more sophisticated arbitration policies with significant network-throughput benefits, and switch traversal, can be performed simultaneously in the same cycle, while still offering energy-delay efficient implementations. [ABSTRACT FROM AUTHOR]

This paper proposes an approach for testing a nanocrossbar switch; fault detection is considered in the presence of faulty switches and nets (of a permanent nature only) in the crossbar. To ensure detection, a one-to-one (onto) relationship in the setting (programming) of the switches is established in each of the configurations of the crossbar. This is accomplished using a constant-sum transformation of the characteristic matrix of the crossbar by utilizing different graph algorithms in O(N^4.5) where N is the matrix dimension. Matrix properties are related to graph algorithms to generate permutation matrices as corresponding to the configurations (phases) of the crossbar. The conditions by which multiple faults are detected by the modified counting sequence (as test set), are proved. Simulation results are provided to further substantiate the validity of the proposed approach to test nanocrossbars of very large dimension and with different switch distribution. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

Over 30 years ago L. Chua proposed the existence of a new class of passive circuit elements, which he called memristors and memristive devices. The unique electrical characteristics associated with them, along with the advantages of crossbar structures, have the potential to revolutionize computing architectures. A well-defined and effective memristor model for circuit design combined with a design paradigm based on well-understood underlying logic design principles would certainly accelerate research on nanoscale circuits and systems. Toward this goal, we propose a memristor crossbar circuit design paradigm in which memristors are modeled using the quantum mechanical phenomenon of tunneling. We use this circuit model to design and simulate various logic circuit designs capable of universal computation. Finally, we develop and present a new design paradigm for memristor-based crossbar circuits. [ABSTRACT FROM PUBLISHER]

Resistive switching with a self-rectifying feature is one of the most effective solutions to overcome the sneaking current issue in a crossbar structure. In this letter, we have successfully demonstrated a prototype device with inherent rectifying property with \a-Si/WO3 bilayer structure. After a forming process, the devices exhibit obvious rectifying property with forward/reverse current ratio of \10^2 at \pm0.75 V and excellent reproducibility. The formation of localized conductive filaments (CFs) in the \WO3 layer and the corresponding CF/a-Si Schottky contact are suggested to explain the rectifying behavior. The results in this letter demonstrate a possible way to realize selector-free crossbar structure. [ABSTRACT FROM AUTHOR]

The crossbar (also called bus matrix) solution is known as one of the most effective communication architectures for modern high-performance embedded systems. To make it even more effective, several topology synthesis methods have been proposed. They mostly generate a crossbar network in a cascaded fashion under the assumption that each crossbar switch is fully connected (i.e., each input has a connection to every output). This assumption often limits optimizing the area efficiency and/or performance of the network due to the unnecessary connections inside the crossbar switches. Some existing methods marginally improve their synthesis results by eliminating the unnecessary connections after the synthesis step. Such postprocessing approaches make sense since considering partially connected crossbar switches earlier in the synthesis flow can greatly increase the optimal topology search space, thereby increasing the runtime. However, the result from these postprocessing techniques is typically far inferior to that from the exhaustive search. In this work, we tackle such limitations of previous methods by introducing a heuristic method based on iterative switch merging. To the best of authors' knowledge, none of previous methods consider the partial connection of crossbar switches in the middle of the topology synthesis. Our experimental results prove the effectiveness of the proposed method by showing up to 30.35 percent of area saving against those methods that consider the partial connection only in a postprocess. The results also show the superiority of the proposed method against the existing topology synthesis methods, showing up to 49.09 percent area saving and synthesis time reduction by several orders of magnitude. [ABSTRACT FROM AUTHOR]