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1500-V photovoltaic (PV) configuration is the standard design in the solar PV industry. Extending the maximum dc voltage from 1000 to 1500 V can reduce the installation cost of the entire power plant. However, it may affect the reliability of the corresponding 1500-V PV inverters, due to the increased loading stresses, i.e., voltage stress and thermal loading of power devices. In this context, this article proposes a solution to the reliability enhancement of silicon carbide-mosfet-based 1500-V PV inverters with variable gate resistance. This solution offers a possibility to adaptively adjust the switching speed to make a compromise between the switching power loss and voltage overshoot during commutation, thus enhancing the reliability. The evaluation results based on the mission profile of a 125-kW 1500-V PV system installed in Denmark indicate that the PV inverter with the proposed design, i.e., variable gate resistance, can improve reliability performance compared to the fixed gate resistance solution while ensuring a safer operating voltage margin. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]