Search

In this paper, low-temperature polycrystalline silicon (poly-Si) tunnel thin-film transistors (tunnel-TFTs) are demonstrated to show excellent short-channel effects immunity due to their special current transport mechanism: inter-band tunneling. The ammonia (NH 3 ) plasma surface treatment before the deposition of gate dielectric can significantly reduce the grain boundary trap state densities (N GB ) of poly-Si channel film and the interface trap state densities (N it ) at the gate-oxide/poly-Si interface. About 27% reduction of N GB by NH 3 plasma surface treatment can reduce the minimum drain current ~ 0.51 × and improve the subthreshold slope due to the suppression of trap-assisted tunneling, which dominates the current transport in the subthreshold operation region. In addition, about 37% reduction of N it by NH 3 plasma surface treatment can significantly enhance the on-state current ~ 2.86 × due to the increase of band bending of poly-Si channel potential, which can decrease the tunneling distance to increase the electron tunneling probability. Consequently, the performance improvement of poly-Si tunnel-TFTs by the NH 3 plasma surface treatment would be helpful for the development of system-on-panel and three-dimension integrated circuits. [ABSTRACT FROM AUTHOR]

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states ( N\mathrm {{it}} ) near the conduction band edge. The ON-state current ( I\mathrm{\scriptscriptstyle ON} ) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N2 plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N\mathrm {it} obviously, which greatly enhances the surface potential modulation by the gate and improves the I\mathrm{\scriptscriptstyle ON} value of poly-Si TFETs \sim 3.7\times . The OFF-state current ( I_{\mathrm { {min}}} ) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of \sim 40 %, because of the passivation of grain boundary trap ( N\mathrm {trap} ) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42\times 10^{5} to 6.13\times 10^6 . In addition, the subthreshold swing, $I_{{\mathrm{\scriptscriptstyle ON}}}$ , and I_{\mathrm { {min}}} of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device. [ABSTRACT FROM AUTHOR]

In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating \n^+ region have better immunity to DIBL. Second, VSA-TFTs with a longer floating \n^+ region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating \n^+ region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating \n^+ region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of VG is less than half of VD. [ABSTRACT FROM AUTHOR]

This paper reports the impacts of \NH3 plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. off-state currents may be improved by increasing the oxide overetching depth. The on/ off current ratio may be also improved by increasing the oxide overetching depth. The \NH3 plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by \NH3 plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing ( < 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. off-state currents can be improved by increasing Lmask, even when the oxide overetching depth and the gate oxide thickness are changed. [ABSTRACT FROM AUTHOR]