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In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship h100iBTO(001)// 〈110〉Ge(001) with the substrate, describing a 45° lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I(001)/ I(002), I(101)/I(002), and I(111)/I(002) derived from ω-2θ scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. [ABSTRACT FROM AUTHOR]

Polycrystalline silicon (pc-Si) thin-films with a grain size in the range of 0.1–100 μm grown on top of inexpensive substrates are economical materials for semiconductor devices such as transistors and solar cells and attract much attention nowadays. For pc-Si, grain size enlargement is thought to be an important parameter to improve material quality and therefore device performance. Aluminum-induced crystallization (AIC) of amorphous Si in combination with epitaxial growth allows achieving large-grained pc-Si layers on nonsilicon substrates. In this work, we made pc-Si layers with variable grain sizes by changing the crystallization temperature of the AIC process in order to see if larger grains indeed result in better solar cells. Solar cells based on these layers show a performance independent of the grain size. Defect etching and electron beam induced current (EBIC) measurements showed the presence of a high density of electrically active intragrain defects. We therefore consider them as the reason for the grain size independent device performance. Besides dislocations and stacking faults, also Σ3 boundaries were electrically active as shown by combining electron backscattered diffraction with EBIC measurements. The electrical activity of the defects is probably triggered by impurity decoration. Plasma hydrogenation changed the electrical behavior of the defects, as seen by photoluminescence, but the defects were not completely passivated as shown by EBIC measurements. In order to reveal the origin of the defects, cross section transmission electron microscopy measurements were done showing that the intragrain defects are already present in the AIC seed layer and get copied into the epitaxial layer during epitaxial growth. The same types of intragrain defects were found in layers made on different substrates (alumina ceramic, glass ceramic, and oxidized silicon wafer) from which we conclude that intragrain defects are not related to the relatively rough alumina ceramic substrates often used in combination with high temperature epitaxy. Further improvement of the material quality, and hence device performance, is therefore not simply achieved by increasing the grain size, but the intragrain quality of the material also needs to be taken into account. For pc-Si layers based on AIC and epitaxial growth, the seed layer has a crucial impact on the intragrain defect formation. [ABSTRACT FROM AUTHOR]

Strontium titanate (STO) is a dielectric with a cubic perovskite type structure and of increasing interest for microelectronics, especially in the metal-insulator-metal (MIM) capacitors due to its high dielectric constant. The dielectric constant of the STO films and consequently the performance of the MIM capacitors appear to be strongly influenced by the process conditions. In this work the authors report on the influence of various thermal treatments upon the crystallinity and morphology of strontium titanate crystals. The influence of spike, laser, or rapid thermal anneals on the morphology with respect to grain size and topography of the crystalline stoichiometric STO films is studied. Also, the use of a stack containing a Sr-rich STO (62% Sr) bottom seed layer and a stoichiometric STO top layer in combination with a thermal treatment was found to affect the microstructure of the STO film. A comparison of the electrical properties for various thermal treatments has been made. [ABSTRACT FROM AUTHOR]

The density of hafnium oxide films grown by atomic layer deposition for high-κ gate dielectric applications was investigated for films with thickness in the nanometer range. The density, measured by combining the film thickness from transmission electron microscopy with the amount of hafnium deposited from Rutherford backscattering, decreased with decreasing film thickness. The dielectric constant of hafnium oxide remained constant with decreasing film thickness, however. The main reason for the decrease in the measured density seemed not to be a decrease in the inherent material density. Instead, the relative importance of interface roughness in the density measurement increased with decreasing film thickness. [ABSTRACT FROM AUTHOR]

The reaction of a Ti (8 nm) capped Co film (15 nm) with a Si[sub 3]N[sub 4] layer (150 nm) is studied after rapid thermal annealing at 660 °C for 120 s in a N[sub 2] ambient. X-ray photoelectron spectroscopy, transmission electron microscopy, electron energy-loss spectroscopy, and Auger electron spectroscopy are used to study the reaction products. Combining the results of the different analyses yields a layer stack consisting of: TiO[sub 2]/TiO/unreacted Co/(Ti,Co)[sub 2]N/Co[sub 2]Si, followed by amorphous Si[sub 3]N[sub 4]. The reaction mechanisms are discussed. Conclusions concerning the risk for degradation of nitride spacers in advanced devices are drawn. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Several applications of two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) in nanoelectronic devices require the deposition of ultrathin pinhole free high-κ dielectric films on 2D TMDs. However, deposition of nm-thin high-κ dielectric films on 2D TMDs remains challenging due to the inert TMD surface. Here, we demonstrate that the surface of a synthetic polycrystalline 2D MoS2 film is functionalized with SiO2 to enable the atomic layer deposition (ALD) of thin and continuous Al2O3 and HfO2 layers. The origins of nucleation, the growth mode, and layer coalescence process have been investigated by complementary physical characterization techniques, which can determine the chemical bonds, absolute amount, and surface coverage of the deposited material. SiO2 is prepared by oxidizing physical vapor deposited Si in air. The surface hydrophilicity of MoS2 significantly increases after SiO2functionalization owing to the presence of surface hydroxyl groups. SiO2 layers with a Si content of only 1.5 x 1015 atoms/cm² enable the deposition of continuous 2 nm thin Al2O3 and HfO2 layers on MoS2 at 300 °C. This fast layer closure can be achieved despite the sub-nm thickness and discontinuity of the SiO2 nucleation layer. On the basis of the experimental results, we propose a nucleation mechanism that explains this fast layer closure. Nucleation of Al2O3 and HfO2 occurs on the SiO2 islands, and fast layer closure is achieved by the lateral growth starting from the many nm-spaced SiO2 islands. Finally, the dielectric properties of Al2O3 on the functionalized MoS2 are confirmed in a top-gated capacitor that shows a leakage current of 3.8 x 10-6 A/cm² at a 3.4 nm equivalent oxide thickness. To conclude, fast nucleation and layer closure in ALD can be achieved even for a sub-nm thin, discontinuous nucleation layer. We propose that this insight can also be applied to other ALD processes, materials, or applications where thin and fully continuous layers are required. [ABSTRACT FROM AUTHOR]

Incorporation of source–drain stressors (S/D) for FinFETs to boost the channel mobility is a promising scaling approach. Typically SiGe:B S/D stressors are used for p FinFETs and Si:C:P S/D stressors for n FinFETs. The deposition of such Si:C:P S/D stressors requires a low thermal budget to freeze the C in substitutional sites and also to avoid problems associated with surface reflow of Si fins. In this work, we report the material properties of Si:C and Si:C:P epitaxial layers grown by chemical vapor deposition, in terms of their defectivity and C incorporation as a function of different process conditions. The undoped Si:C layers were found to be defect free for total C contents below 1%. Above this concentration defects were incorporated and the defect density increased with increasing C content. Abrupt epitaxial breakdown occurred beyond a total C content of 2.3% resulting in amorphous layers. P doping of Si:C layers brought down the resistivity and also thicker Si:C:P films underwent epitaxial breakdown. Additionally, the use of nitrogen instead of hydrogen as carrier gas resulted in an increase of the growth rate and substitutional C incorporation both by a factor of two, while the surface defect density reduced. [ABSTRACT FROM AUTHOR]