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Dopingless Tunnel Field Effect Transistor is a prominent device because of its low sub-threshold swing and fast switching speed. In this paper, DL-TFET is investigated for enhancing the performance parameters by applying different engineering techniques. The hetero-junction is implemented in the DL-TFET for increasing the ION current. Further, for reducing the ambipolar current and enhancing the ON-characteristics by introducing the non-uniform oxide layer, hetero-gate and then further optimization is done by varying the "x" compositions of In1-xGaxAs for source side material. The various staggered hetero-gate hetero-junction DL-TFET structures with different EBeff are comparatively investigated for analyzing their performance parameters. Among them, highly staggered Hetero-junction DL-TFET with EBeff = 0.374 eV shows better performance as lower threshold voltage, higher ION current, high transconductance and lower sub-threshold swing. So, the In0.45Ga0.55As/In0.25Ga0.75As based hetero-gate at TG = 4.2 eV and Θ = 7.59° heterojunction DL-TFET structure can be chosen for fast switching and advanced circuit application. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of AlGaN/GaN MOS-HEMT based pH sensor for the first time to determine pH of different electrolyte solutions. Gouy-chapman stern model has been used to calculate the surface charge density. The results obtained using analytical model have been verified and show good agreement with the simulated results. Cavity length, thickness of AlGaN barrier layer and Al composition have been optimized to improve the sensitivity of the device. It has been observed that the drain current and threshold voltage decreases with increase in pH of the electrolytic solutions. Proposed AlGaN/GaN MOS-HEMT sensor demonstrate a quick response to the pH changes. The maximum drain-on-sensitivity of the device is 132mA/mm-pH. Surface potential and threshold voltage sensitivity of 0.95mV/pH and 950mV/pH respectively have been obtained which is much higher than the Nernstian limit(59.2mV/pH). [ABSTRACT FROM AUTHOR]

This paper examines the DC performance of Dual-Gate MISHEMT with different substrate material such as sapphire, silicon carbide SiC, and silicon. The performance parameters evaluated are threshold voltage, drain current, transconductance, and drain conductance. It is observed that DG-MISHEMT with the sapphire substrate and HfO2 gate dielectric results in positive threshold voltage shift from −4.7 to −3.8 V(∼19%) and also degrades the drain current as compared to the device with silicon nitride gate dielectric due to the reduced channel charge concentration. But the device with HfO2/Al2O3 gate stack maintains 182 mA/mm of IDS along with a positive threshold voltage shift of 14.8% as compared to DG-MISHEMT with Si3N4 gate dielectric and sapphire substrate. A similar performance has been observed with Dual-Gate MISHEMT with SiC and silicon substrate. The device, having the silicon substrate and HfO2/Al2O3 gate stack, shows a positive threshold voltage shift of ∼53%, but as a trade-off the drain current reduces to 158 mA/mm as compared to 183 mA/mm of the device at low drain bias with the sapphire substrate and Si3N4 gate dielectric. [ABSTRACT FROM AUTHOR]

In this paper, an extensive investigation of low-frequency (1/f) noise and total ionizing dose–response of junctionless accumulation mode double-gate (JAM DG) MOSFET is presented. Current–voltage (Id–Vg) characteristics and low-frequency noise of JAM DG MOSFET are simulated at different ionized doses and compared to different gate oxide thickness and different channel doping concentrations. A significant amount of irradiation-induced threshold voltage shift and increase in low-frequency noise is observed for different gate oxide thickness and channel doping concentration. Moreover, the irradiation-induced border trap densities are also obtained at different doses. The gamma radiation model of Sentaurus TCAD is used to get the required results. [ABSTRACT FROM AUTHOR]

A junctionless double gate radiation sensitive FET (RADFET) has been proposed to improve the radiation sensitivity and its application as CMOS-based dosimeter is discussed. Analytical model has been developed from 2D Poisson equation using variable separation technique and electrical performance of the proposed architecture has been compared with the conventional double gate (DG) RADFET. The comparison of device characteristics shows that the JL DG RADFET exhibits better electrical performance and sensitivity as compare to conventional DG RADFET. The model is verified using ATLAS 3D device simulation software. [ABSTRACT FROM PUBLISHER]

In this paper, using a 2-D Poisson equation (in cylindrical coordinates), an analytical drain current model of a nanoscale RingFET architecture has been developed for the first time. Major short-channel effects, such as channel length modulation, velocity scattering, and drain-induced barrier lowering, are taken under consideration while developing the model. A bandgap narrowing model has been employed to investigate the impact of higher channel doping. The modeled results of the surface potential, electric field, threshold voltage ( V\mathrm{ th} ), subthreshold slope, and drain current have been verified by comparing with those of the ATLAS 3-D device simulation. The influence of the drain radius and position of the source/drain regions on the electrical characteristics of the device has also been demonstrated. [ABSTRACT FROM PUBLISHER]

In this paper, an analytical model of a four-gate dielectric modulated MOSFET for label-free electrical detection of the biomolecules has been proposed. To provide a binding site for the biomolecules, the channel region of MOSFET is left open in the four-gate configuration, which is conventionally covered by the gate electrode. As a result, the electrical characteristics of the device are affected by the neutral and charged biomolecules that binds to the underlap (open) channel region. The electrostatics is developed by solving a 2-D Poisson’s equation, assuming a parabolic potential profile along the channel direction using the conformal mapping technique and subsequently the drain current model is developed. The change in the threshold voltage is used as a sensing metric for the detection of biomolecules after their immobilization in the open region. The characteristic trends are supported and verified using the ATLAS device simulation software. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage analysis of junctionless nanowire transistor (JNT) due to radiation/ process/stress/hot-carrier damage-induced localized/fixed charges at elevated temperatures is discussed. A temperature-dependent threshold voltage model for JNT with localized charges has been developed including the source/drain depleted regions. The impact of position, density, and polarity of localized charges on channel potential, bandgap energy, and threshold voltage is studied. Four different localized charge density profiles have been used to evaluate the performance degradation. The results demonstrate that localized charges significantly change the device threshold voltage and temperature sensitivity and show less detrimental effect at elevated temperatures. [ABSTRACT FROM AUTHOR]

The paper presents a comprehensive comparison study of p-i-n and p-n-p-n tunnel field-effect transistor (TFET) architectures and the impact of temperature on their dc and circuit performance. The impact of a hetero-gate (HG) dielectric on the circuit performance also forms the part of the study. The device performance of p-i-n and p-n-p-n TFET with high-k dielectric and HG dielectric and the effect of temperature on the drain current characteristics, Ion/Ioff, and threshold voltage has been investigated and compared with MOSFET. Furthermore, the variations in the inverter (n-TFET with resistive load) transient characteristics and the fall delay due to temperature variations are studied using mixed mode simulations carried out with ATLAS device simulation software. Results reveal that TFET exhibits weak temperature dependence when the current conduction is band-to-band tunneling dominated, while the temperature dependence increases in the off-state regime, and the fall delay of resistive load n-TFET inverter decreases with increasing temperature. [ABSTRACT FROM PUBLISHER]

In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-\kappa), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with DMG, i.e., GS dual-material DG (GSDMDG), have been taken into consideration. The simulation results demonstrate that, out of the several design engineerings, the GCGSDG is the most suitable for high-speed switching applications. However, the GSDMDG provides superior performance as an amplifier. [ABSTRACT FROM PUBLISHER]

The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure. [ABSTRACT FROM AUTHOR]

A new analytical threshold voltage model for InAlAs/InGaAs heterostructure, InP based HEMT has been developed considering the short-channel effect in subthreshold regime. The model is developed following the MESFET analysis, considering fully depleted InAlAs region as two isolated depletions––one due to metal–semiconductor contact and other due to transfer of carriers from InAlAs region to the 2DEG quantum well. Poisson’s equation is solved using Green’s Function technique and the solution is then verified by comparing it with Numerical technique. The 2D threshold voltage obtained from our analysis was found to be in good agreement with 1D threshold voltage for higher gate lengths, thus proving the validity of our model. [Copyright &y& Elsevier]

A new analytical model for InAlAs/InGaAs heterojunction, InP based high electron mobility transistor (HEMT) incorporating the depletion effect in the InAlAs region is developed and extended to predict sheet carrier density, the effect of parallel conduction through variation of depletion width, potential at the interface of depletions and ΔEc−Ef with gate voltage. The sheet carrier density obtained shows excellent agreement with the available results and gives a new solving procedure for HEMT from MESFET analysis. [Copyright &y& Elsevier]

A study based on the numerical simulation of Double Gate JunctionLess Transistor DG-JLT has been presented under the influence of Trap Charges (TC) inside the oxide or at the oxide/channel interface using ATLAS TCAD software. These trap charges may be generated due to various effects like aging and exposure to radiation and chemical environment etc. and thus leading to variability in the device behavior. To evaluate the impact of TC, the forward and reverse threshold voltage were calculated by altering the gate voltage from zero to positive and subsequently returning to zero, while employing various gate bias durations. Asymmetric doping has also been employed to study the variability in DG-JLT with TC as compared to Uniformly Doped DG-JLT (UD-DG-JLT). Furthermore, the investigation is expanded to evaluate how the performance of AD-DG-JLT is affected by the Dual Material Gate (DMG) in the presence of generated TC. To explore the robustness of the device, breakdown voltage (BV) has been examined with varying TC and device specifications. The impact of the trap energy level (E C -E T) on the BV of the devices has also been explored. Extensive numerical simulations have also been performed to showcase the results regarding the change in drain current caused by Single Event Upset (SEU). • The influence of TC on the AD-DG-JLT is computed due to the applied gate bias stress. • The AD-DG-JLT (72 %) provides higher BV as compared to UD-DG-JLT. • DMG architecture further increases the device BV (35 %) and variability with TC. • The observed change in DMG-AD-DG-JLT architecture due to SEU is higher. [ABSTRACT FROM AUTHOR]

This paper presents a TCAD based investigation of virtually fabricated Π-shaped Gate p-GaN HEMT for reliable enhancement mode operation. A detailed comparison with the Conventional T-Gate counterpart, with a focus towards the trap related dispersive effect reveals the superiority of Π-shaped Gates P-GaN HEMT for suppressing both the vertical substrate and gate leakage currents, thereby enhancing the breakdown characteristics of the device. A modification of the electric fields, into a stepped profile, demonstrates effective suppression of the leakage through the surface defects, and spillover into GaN buffer, thereby mitigating the trap related dispersive effects. Dispersive effect of the two devices has also been compared using current Slump Ratio (SR) which is lower for Π-shaped Gate P-GaN HEMT. Further analysis into laterally scaled drain-access regions, demonstrates superiority of Π-shaped Gates in achieving a reliable thermal operation, and applicability of Π-shaped Gate P-GaN HEMT for future RF and High Power applications. • Π – Shaped Gate results in an improvement of reverse breakdown and thermal profile ensuring reliability for p - GaN devices. • A parallel arrangement of MS Schottky diodes improves the current handling capacity of the p – GaN layer with a Π – Gate. • Π – Gate limits the leakage of electrons through the surface defects and suppresses the trap related gate – lag phenomenon. • Pulsed IV of Π - Gate reveals significantly suppressed trap – related dispersive effects for laterally scaled devices. • Field modification due to Π – Gate limits hole deficiency in p - GaN layer and improves the threshold voltage instability. [ABSTRACT FROM AUTHOR]

In this work, a physics based analytical model has been proposed for an open gate AlGaN/GaN HEMT for electrical detection of biomolecules-uricase, glucose, biotin and cytochrome -c. The proposed device is easy to fabricate and offers high sensitivity at low operating voltages as complete gate area has been used for immobilizing biomolecules. The analytical model has been developed for evaluating drain current sensitivity and threshold voltage sensitivity by considering that the gate electrode is immersed in solution of de-ionized (DI) water. Results obtained by analytical model are in good agreement with previously reported experimental data and have also been verified with simulation results. Detailed sensitivity analysis has been carried out by evaluating additional electrical parameters such as gate-source capacitance, channel potential, channel conductance and transconductance to detect the presence of biomolecules. Barrier thickness, channel width to length ratio (W/L sd) and Al composition in barrier layer have been optimized to obtain high sensitivity. The maximum drain current and threshold voltage sensitivity obtained for uricase is 3.95 × 108 and 820 mV respectively. • A physics based analytical model has been developed for detection of biomolecules using open gate AlGaN/GaN MOS-HEMT. • Due to the superior properties of AlGaN/GaN MOS-HEMT it shows high sensitivity for polar liquids. • The maximum drain current and threshold voltage sensitivity obtained for Uricase is 3.95×108 and 820mV respectively. • The proposed sensor uses open gate surface for biomolecule immobilization, therefore it is easy to fabricate. [ABSTRACT FROM AUTHOR]

Abstract: In the present paper a temperature dependent analytical model for poly-crystalline silicon TFT incorporating the short channel effects and inverse narrow width effects is developed. The temperature dependent modeling parameters and the effect of fringing capacitances are considered to evaluate the drain current, transconductance and cut-off frequency etc. The effect of change in mobility with gate voltage has also been incorporated and the results so obtained show excellent match with the experimental results thus proving the validity of our model. [Copyright &y& Elsevier]

This paper presents an analytical 2D model for InAlAs/InGaAs/InAlAs/InP LMHEMT that explains the drain induced barrier lowering (DIBL) and its effect on the device performance. The increasing drain voltage lowers the potential barrier between source and drain in or near the subthreshold region. As the barrier is lowered to be comparable to the thermal energy the device begins to conduct again. This effect causes the threshold voltage control problem and degrades the device performance. The model is used to obtain the potential distribution and the electric field in the depletion region and the threshold voltage is also calculated from the minimum channel potential. It is proposed as a consequence of the analysis that the device degradation due to DIBL effect is a very short channel problem. [Copyright &y& Elsevier]

This work investigates the influence of Single Event Transient (SET) effect on Double Channel Dual Gate (DC-DG) AlGaN/GaN HEMT using TCAD simulations. Both Single Channel (SC) and Double Channel HEMT have been calibrated with reported experimental results and further extended by introducing a second gate in the structures to analyze its sensitivity towards heavy ion strike. The effective gate length has been optimized in such a way that the saturation currents and threshold voltage of dual gate devices is similar to that of the single gate devices. The DC-DG HEMT improves the heavy ion sensitivity, thus making it a more viable device for sensing application (mainly radiation). Different biases and gate materials have been used to observe the influence of SET on the DC-DG AlGaN/GaN HEMT. Further, the impact of the graded AlGaN barrier on the device current as well as on the sensitivity of the DC-DG HEMT towards SET is studied. To ascertain the performance of DC-DG HEMT for dosimeter applications, its sensitivity toward heavy ion impact in switched mode is monitored. Investigation reveals that the device current returns to its original order of magnitude after every ion impact, and therefore can be effectively used as a dosimeter. • This work investigates the impact of heavy ion particle strike on Double Channel – Dual Gate (DC-DG) GaN HEMT for sensing applications. • The DC – DG architecture is highly sensitive to the heavy ion induced Single Event Effects (SEEs), making it ideal for heavy ion sensing. • The sensitivity of the DC – DG architecture, is further enhanced by incorporating graded AlGaN layer for the second channel. • To validate the device sensitivity, the performance of DC – DG architecture is evaluated in a switched mode operation in presence of heavy ion strikes. [ABSTRACT FROM AUTHOR]

In the present work, a novel device architecture Skin Deep Insulated Extension-RingFET (i.e. SDIE-RingFET) has been reported that incorporates the better known dielectric pocket in RingFET architecture. Various analog performance matrices like I ON /I OFF , V th roll off, Sub-threshold slope (SS), Device efficiency (g m /I ds ), conduction band energy (CBE) and electron temperature (T E ) have been studied to investigate the impact of Skin Deep Insulated Extension (SDIE) on RingFET architecture. Insulated extension enhances the immunity of the device against Short Channel Effects by reducing I OFF and providing a higher I ON /I OFF ratio apart from improved threshold voltage roll-off. In addition, SDIE also prevents dopant diffusion from source/drain to bulk, thereby alleviating the bulk punch-through effect and hence DIBL. [ABSTRACT FROM AUTHOR]

In this work, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates. The authenticity of proposed model for GCE-RingFET architecture has been justified by comparing the analytical results with simulation results obtained using ATLAS 3D device simulation. Performance comparison of GCE-RingFET with the conventional RingFET device architectures has been performed. Various important performance metrics such as surface potential, transfer characteristic (I ds -V gs ), I ON /I OFF ratio, Threshold voltage roll off, Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Trans -conductance Generation Efficiency (g m /I ds ), have been investigated. [ABSTRACT FROM AUTHOR]

In this paper, drain current model has been formulated for Double Gate (DG) p-n-i-n Tunnel FET (TFET) using Lambert-W function. The model includes the impact of mobile charges, gate dielectric thickness (t ox ) and channel thickness (t si ) on quasi fermi level, gate threshold voltage (V TG ), onset voltage (V Gonset ) and Tunneling Barrier Width (TBW) over the entire operating range i.e. accumulation to inversion state. Important electrostatic and electrical parameters such as the effective potential (φ effective ) at the center of the channel, 2-D channel potential, electric field, energy band profile and Tunneling Barrier Width (TBW) dependent drain current have been modeled. Moreover, gate and drain bias controllability in different operating regimes has also been investigated by varying oxide thickness (t ox ), channel thickness (t si ), intrinsic channel length (L int ) and at different temperatures. Important FOMs required for analog circuit performance such as transconductance (g m ), drain conductance (g d ), output resistance (R out ), early voltage (V EA ) have also been evaluated and verified using ATLAS device simulation software. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model for Junctionless (JL) Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) based biosensor for label free electrical detection of biomolecules like enzyme, cell, DNA etc. using the Dielectric Modulation (DM) technique has been developed. The analytical results are validated with the help of “Sentaurus” device simulation software. For the biomolecule immobilization, nanogap cavity is formed in the JL MOSFET by etching gate oxide layer from both source as well as drain end of the channel. As a result, the surface potential in the channel underneath the nanogap cavity region is affected by the neutral and charged biomolecules that binds to SiO 2 adhesion layer in the cavity. The surface potential solution is obtained by solving a 2-D Poisson’s equation assuming parabolic potential profile in the channel. The shift in threshold voltage and drain current of the device has been considered as the sensing metric for detection of biomolecules under dry environment condition. [ABSTRACT FROM AUTHOR]

Abstract: An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model. [Copyright &y& Elsevier]

Highlights: [•] A temperature dependent model is developed for GAA MOSFET having localized charges. [•] Analytical results are verified with simulation results of ATLAS 3D simulator. [•] Variations in temperature sensitivity due to localized charges are studied. [•] Degradation is higher at low temperatures and in subthreshold region. [ABSTRACT FROM AUTHOR]

Abstract: In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal–insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n+-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268–2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal–Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534–2540] are also being fabricated these days, mainly at the drain end (-gate) having Metal–Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal–Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189–198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model. [Copyright &y& Elsevier]

Abstract: A simple and accurate analytical model for the threshold voltage of AlGaN/GaN high electron mobility transistor (HEMT) is developed by solving three-dimensional (3-D) Poisson equation to investigate the short channel effects (SCEs) and the narrow width effects present simultaneously in a small geometry device. It has been demonstrated that the proposed model correctly predicts the potential and electric field distribution along the channel. In the proposed model, the effect of important parameters such as the thickness of the barrier layer and its doping on the threshold voltage has also been included. The model is, further, extended to find an expression for the threshold voltage in the sub-micrometer regime. The accuracy of the proposed analytical model is verified by comparing the model results with 3-D device simulations for different gate lengths and widths. [Copyright &y& Elsevier]

Numerical assessment of Dual-Gate AlGaN/GaN MISHEMT have been presented in this paper. Analytical model has been developed and the various parameters extracted are surface potential, electric field and threshold voltage for different device specifications. Threshold voltage of nearly 0.15 V has been computed which is nearly same to that of simulated Dual-Gate MISHEMT. Simulations have been performed using ATLAS TCAD tool. Dual-Gate MISHEMT with different gate dielectric materials such as Si 3 N 4 and gate stack combinations like HfO 2 /Al 2 O 3 has been analyzed. From the results it has been inferred that at higher temperature, drain current and transconductance reduces due to lower electron sheet concentration. Different combinations of gate biases (applied at the second gate i.e. Gate 2 presented near the drain side) has been used for optimizing the device parameter for better switching performance. For DG-MISHEMT with barrier thickness of 22 nm (both the gates connected together), I ON /I OFF ratio reduces from 109 to 106 for high temperature (upto 423 K) due to reduced sheet carrier concentration. For inductance load, output drain voltage exhibits voltage range of 9.2V/2.3V for gate pulse of -8V/+2V with 30% duty cycle. Also, it is seen that as barrier thickness is varied from 18 nm to 30 nm, I OFF increases and results in reduced output drain voltages. Performance of Single Gate and Double Gate MISHEMTs has also been compared for DC-to DC converter using inductance load circuit. • Analytical model for Dual-Gate AlGaN/GaN MISHEMT. • Temperature based investigation upto 500K for Dual-Gate AlGaN/GaN MISHEMT. • Effect of barrier thickness on the I ON /I OFF ratio has been investigated. • DC-to-DC converter using Dual-Gate AlGaN/GaN MISHEMT and inductor load. [ABSTRACT FROM AUTHOR]

In this paper, effect of gamma radiation on SOI-based Tunnel Field Effect Transistor and its application as radiation dosimeter has been investigated. Throughout the paper, the exhaustive simulations have been carried out in order to investigate the generation of the electrons and holes in the oxide region and to anticipate the characteristics of the device from subthreshold region to strong accumulation/inversion region. It is found that under the radiation environment, the radiation induced degradation in threshold voltage shift and interface trap charge could not be ignored. It is concluded that the impact of radiation is visible in the subthreshold region of the drain current than on-state of drain current. Moreover, the radiation characteristics of SOI TFET have been compared with SOI MOSFET to assess its application as a dosimeter. In order to obtain the radiation characteristics of the SOI TFET, Gamma radiation model of sentaurus TCAD has been used. • Impact of gamma radiation on SOI TFET is investigated using gamma radiation model of sentaurus TCAD. • Impact of radiation is more visible in the subthreshold region than in on-state of drain characteristics. • The magnitude of threshold voltage shift in SOI TFET is order of mV. • The electrical characteristics of SOI TFET have been compared with SOI MOSFET. [ABSTRACT FROM AUTHOR]