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Carbon nanotubes (CNTs) have great potential for future high-performance and energy-efficient transistor technology. To realize this potential, methods to dope the CNTs need to be developed to achieve low parasitic resistance of the transistor. Two key issues present themselves: (a) understanding the doping mechanism of the various methods and (b) stability of the doping method. For instance, although studies on molybdenum oxide (MoOx) demonstrate its ability to heavily dope nanomaterials, the interaction between MoOx and the CNT is unclear. Here, we observe an unstable effect of MoOx on the CNT and demonstrate dielectric passivation as a means to preserve the doping strength. The semiconducting CNTs exhibit greater than 103× reduction in resistance after stably doped with MoOx. By exploiting the instability of MoOx, we delve deeper into clarifying the doping mechanism. The relationship between the time-dependent material property of MoOx and the change in the electrical measurements of CNT devices is investigated to study the role of work function in doping the CNTs. We conclude that the doping mechanism of MoOx on the CNT is due to bandgap modulation by charge transfer, which occurs due to the difference in work function between MoOx and the CNT. [ABSTRACT FROM AUTHOR]

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between contact metal and CNT impacts both contact resistance and leakage current. The physical mechanisms underlying the effects are analyzed. A model with calibrated metal coupling strength from experimental data projects ION-IOFF design space to understand the trade-off between shrinking contact and extension lengths. For CNT with diameter of 1 nm, both contact and extension lengths greater than 8 nm are a good compromise between ION and IOFF for digital logic in advanced technology nodes. [ABSTRACT FROM AUTHOR]

Using the reduced resistor network developed in Part I of this two-part article, we present practical design guidelines from device to architecture levels to achieve ultrahigh-density 3-D vertical resistive switching memory (VRSM). We first design both hexagon and comb arrays using 7-nm FinFET as pillar driving transistors (pillar drivers). Small-footprint pillar drivers are necessary for a high pillar areal density competitive to 3-D NAND. We then organize the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) to maximize array efficiency and chip density. We investigate the memory and selector requirements, tolerance of parasitic resistances, latency, and energy consumption for both hexagon and comb architectures. The results indicate that the hexagon array with large low-resistance state (LRS) and nonlinearity (NL) is required for ultradense 3-D VRSM. Compared to the comb array, the hexagon array benefits from a continuous WP pattern and yields a better tolerance of parasitic resistances and a smaller latency. The energy consumptions of both architectures are similar. Compared to the most advanced 3-D NAND, 3-D VRSM has higher chip density and shows better potential for future ultradense storage. [ABSTRACT FROM AUTHOR]

Schottky barrier height modulation in metal/Ge Schottky junction was demonstrated by inserting an ultrathin interfacial silicon nitride layer. The SiN interfacial layer suppressed strong Fermi level pinning in metal/Ge Schottky junction, which resulted in effective control of Schottky barrier height. Metal/SiN/Ge Schottky diode was systematically investigated in terms of SiN thickness dependence and metal work function dependence. At an optimal SiN thickness, Ohmic contact between metal and Ge was obtained as a result of Fermi level depinning, and almost ideal Schottky barrier height determined by the work function difference between the metal and Ge was achieved. This technology was finally applied to metal source/drain Ge metal-oxide-semiconductor field-effect-transistors with low source/drain resistance. [ABSTRACT FROM AUTHOR]

Control of cation injection into the switching layer of conductive-bridge random access memory (CBRAM) during switching is a critical factor for CBRAM reliability. Although extrinsic approaches such as the insertion of a transistor in series have proven effective, solutions intrinsic to the CBRAM itself, which are desired for high density cross-point or 3-D vertical memory arrays, are quite limited. In this letter, we show the significant improvement of cycling endurance for Cu-based CBRAM by scaling the switching layer area down to 30 nm in diameter. Further study suggests that the injection of excessive Cu ions into the switching layer is suppressed owing to spatial limitation during the formation of the conductive filament. These results indicate that the area scaling of the switching layer is an effective solution for achieving highly reliable CBRAM devices. [ABSTRACT FROM PUBLISHER]

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are promising candidates for transistors and interconnects for nanoelectronic circuits. Although CNTs intrinsically have excellent electrical conductivity, the large contact resistance at the interface between CNT and metal hinders its practical application. Here, we show that electrical contact to the CNT is substantially improved using a graphitic interfacial layer catalyzed by a Ni layer. The p-type semiconducting CNT with graphitic contact exhibits high on-state conductance at room temperature and a steep subthreshold swing in a back-gate configuration. We also show contact improvement to the semiconducting CNTs with different capping metals. To study the role of the graphitic interfacial layer in the contact stack, the capping metal and Ni catalyst were selectively removed and replaced with new metal pads deposited by evaporation and without further annealing. Good electrical contact to the semiconducting CNTs was still preserved after the new metal replacement, indicating that the contact improvement is attributed to the presence of the graphitic interfacial layer. [ABSTRACT FROM PUBLISHER]

We present analyses for ACCNT (pronounced as “accent”), which is a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high ON–OFF ratios while preserving current drive. We analyze the ACCNT methodology in terms of its tradeoffs and explore optimizations that may serve as future design guidelines. We also investigate circuit-level considerations and the impact of density variation on the ACCNT design. We find that ACCNT can improve the yield of a one-million transistor chip from 0% (conventional CNT design) up to 99% at a cost of \3.3\times area overhead if the fraction of semiconducting CNTs is improved to 99.9%. [ABSTRACT FROM PUBLISHER]

In this brief, the impact of parasitic resistance and capacitance on InGaAs HEMT digital logic circuits is investigated via device simulations and circuit analysis. We present the correlation between device geometry and circuit delay for various structural scenarios. When the gate-to-S/D contact distance Lsg is scaled down to logic device standards, high integration density and additional circuit performance can be expected as compared with experimental devices that are demonstrated to date. This brief highlights the importance of engineering the device structure outside the channel region to achieve high device performance and device density. Scaled InGaAs HEMTs show superior performance over experimental devices and 27% less power consumption for the same circuit-speed constraint. [ABSTRACT FROM AUTHOR]

Carbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. The following two fundamental challenges prevent the fabrication of CNFET circuits with the aforementioned advantages: 1) misaligned and mispositioned CNTs and 2) metallic CNTs. Misaligned and mispositioned CNTs can cause incorrect functionality. This paper presents a technique for designing arbitrary logic functions using CNFET circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mispositioned CNTs. Experimental demonstration of misaligned and mispositioned CNT-immune logic structures is also presented. [ABSTRACT FROM AUTHOR]

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic CV/I gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance. [ABSTRACT FROM AUTHOR]

This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance Cgg is decomposed into three major components: 1) capacitance Cgc between the gate and the parallel cylindrical conducting channels (the number of channels ≥ 1) in dual-layer dielectric materials; 2) outer fringe capacitance Cof between the gate and the source/drain cylinder conductors; and 3) coupling capacitance Cgtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed. [ABSTRACT FROM AUTHOR]

In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input NAND gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications. [ABSTRACT FROM AUTHOR]

Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors, NiSi-gate workfuncfion control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi2. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance. [ABSTRACT FROM AUTHOR]

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption. [ABSTRACT FROM AUTHOR]

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106. Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state. [ABSTRACT FROM AUTHOR]