Search

Overcoming the drawbacks of the existing ferroelectric tunnel junction (FTJ) models which ignore the dynamic or multi-domain switching behaviors, we develop a more comprehensive FTJ model by combining the Time-Dependent Landau-Ginzburg (TDLG) equations to solve the multi-domain dynamic switching of ferroelectric layer and the Non-Equilibrium Green Function (NEGF) to solve the tunneling current. The model successfully reproduces the experimental results of our fabricated metal-ferroelectrics-insulator-semiconductor (MFIS) FTJ. This model empowers us to predict both the dynamic and multi-state switching of FTJ, showing its promise for applications in the high-density data storage and analog computing. [ABSTRACT FROM AUTHOR]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]

We report the ultimate performance of a double-gate ultrathin body (DG-UTB) FET employing materials from group IV, III-V, and 2-D materials based on International Technology Roadmap for Semiconductors (ITRS) projected specifications for high-performance (HP) and low-power (LP) technologies. The band structures of the channel materials were obtained using the sp ^3\textd^5\texts^\ast tight binding model and the first-principles density functional theory. The ballistic performance of FETs designed based on the ITRS specifications for 2018 and beyond was evaluated via the semiclassical ballistic transport model. The leakage current due to direct source-to-drain tunneling was calculated based on Wentzel–Kramers–Brillouin approximation. For nFET used in the HP technology, GaSb nFET has the best voltage scalability followed by Ge nFET in 2026. It was found that I\mathrm{\scriptscriptstyle ON} of InAs and In0.3 Ga0.7Sb nFETs is among the lowest, and they require larger power supply voltage ( V\mathrm{DD} ) among III-V semiconductors considered to achieve I\mathrm{\scriptscriptstyle ON} of silicon nFET. However, they show lower power delay product (PDP) due to their smaller electron effective mass, resulting in higher carrier velocity. Ge pFET offers the best voltage scalability for pFET used in the HP technology. For the voltage scalability assessment based on the requirements for the LP technology, MOSFETs based on Si offer better performance in terms of I\mathrm{\scriptscriptstyle ON} and PDP than MOSFETs based on 2-D materials. Among the 2-D materials studied, black phosphorus and silicane MOSFETs exhibit higher I\mathrm{\scriptscriptstyle ON} and better voltage scalability and PDP. [ABSTRACT FROM AUTHOR]

We present a computational study of the device performance of graphene nanoribbon tunneling field-effect transistors (TFETs) with a heterogeneous channel. By varying the length and the energy bandgap (EG) of the heterogeneous region, the on- and off-state currents ( ION and IOFF) can be effectively optimized independently. Both semiconducting and semimetallic heterogeneous regions are studied to understand the effects of EG engineering on device behaviors. In addition, the effect of gate coverage (GC) over the heterogeneous region is also investigated. We found that device performance is greatly affected by the positioning of the gate to modify the region where band-to-band tunneling occurs. For a given ION/IOFF of eight orders, our results show that, for the semiconducting heterojunction, a higher ION can be obtained by having the gate partially covering the heterogeneous region. This is due to a combination of a short tunneling length and resonant states, which leads to an increase in carrier concentration for the tunneling mechanism. On the other hand, for the semimetallic case, a similar ION/IOFF is only attainable when the heterogeneous region is not covered by the gate. A large I \rm OFF is observed for even small GC due to the valence electrons from the source traveling to the conduction bands of the semimetallic region, enhancing the carrier transport toward the drain. Our study highlights the device design consideration required when optimizing the device performance of heterojunction TFETs. [ABSTRACT FROM PUBLISHER]

We present a detailed simulation study on the current–voltage characteristics of ballistic graphene nanoribbon (GNR) tunneling FETs of different widths with varying temperatures and channel length. Our model uses the self-consistent nonequilibrium Green's function and the quasi-2-D Poisson solver with the material details of the GNRs modeled by the uncoupled mode space Dirac equation. We find that, in general, the GNR tunneling FETs from the \3p + \1 family have better ION/IOFF characteristics than those from the \3p family due to smaller effective masses of the former. A lower drain doping concentration relative to that of the source enhances the ION/IOFF. Most significantly, we find that a higher doping concentration at the source enhances ION but degrades the subthreshold swing (SS). As a function of temperature, the SS shows highly nonlinear behaviors. In terms of intrinsic delay and power-delay product, the GNR tunneling FETs show very promising scaling behaviors and can be optimized to meet the International Technology Roadmap for Semiconductors roadmap requirements through adjustment in doping concentrations and other parameters. [ABSTRACT FROM PUBLISHER]

The effect of 2-D electrostatic environment on the device performance of ultimately thin-body tunneling field-effect transistors (UTB-TFETs) using graphene nanoribbons (GNRs) is investigated by varying the gate-oxide thickness and insulating material with different dielectric constants (k). Compared to Si TFETs with different body thicknesses, the atomic-layer-thick structure enhances the lateral fringing fields at the source–channel interface, resulting in a lower on-state current in GNR TFETs with high-k oxide as compared to the low-k variant of the same thickness. Low- k spacers are therefore essential to counter this effect and reap the benefits of high-k dielectrics in improving the device performance of UTB-TFETs. [ABSTRACT FROM AUTHOR]