Search

The FFT is enumerate is DFT and DFT is enumerate is consecutive way, it accomplishes continuous application with constant preparing when the information is persistently taken care of through the processor. Included paper, joined is radix-2 butterfly (R 2 B), R 4 B & R 8 B components based single path delay feedback (SDF) and modified carry select adder (MCSLA) technique, for diminishing the computational stages and for decreasing the equipment use than the R2B and R 4 B FFT. The implemented SDF technique has single delay commutators at one stage without exception. N/2 point is consecutive controlled in consequence of delay component. The proposed technique has less number of multipliers and the more modest number of computational stages and butterfly components than the Radix-2 & 4 FFT.

This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.

This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier-based double throughput MAC.

2-D-to-3-D conversion is one way to make full use of 2-D contents to produce 3-D contents. Real-time 2-D-to-3-D conversion is required for 3-D consumer electronic devices, which demands fast processing speed especially for high-definition videos. In this paper, we propose a reconfigurable VLSI architecture for real-time 2-D-to-3-D conversion. Two different depth-retrieval methods are implemented in this architecture in order to support the choice of a best method or combination of different methods. The proposed architecture can also support different resolutions (4K, 1080p, and 720p) and the original view can be configured as either left view or right view. In order to overcome the problem of “Memory Wall”, we propose a data reuse method to reduce memory traffic for the proposed architecture so that the overall performance is improved to realize real-time conversion. The experiment result shows that the implemented 2-D-to-3-D architecture can achieve state-of-the-art throughput (4K@30f/s).

In this work, VLSI architectures with less delay/area for lifting based DWT are proposed.The proposed logic used for area efficient DWT is to perform the whole operation with one processing element.The proposed logic used for delay efficient DWT is to perform the whole operation with multiple processing elements in parallel.In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. In this paper, high performance VLSI architectures for lifting based 1D and 2D-Discrete wavelet transforms (DWTs) are proposed. The proposed logic used for area efficient lifting based DWT is to perform the whole operation with one processing element. Similarly, the proposed logic used for delay efficient lifting based DWT is to perform the whole operation with multiple processing elements in parallel. In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. The proposed and existing lifting based 1D and 2D lifting based DWTs are implemented with 45źnm technology. The results show that the proposed designs achieve significant improvement compared with existing architectures. For example, 9-point 2-parallel proposed (9, 7) single level 1D-DWT achieves 33.5% of reduction in total cycle delay compared with direct form. Similarly, 9-point single PE proposed (9, 7) single level 1D-DWT achieves 59.8% and 75.5% of reduction in total area and net power over direct form respectively.

This work presents new flexible-architecture for maximum-a-posteriori (MAP) decoder with multi-radix modes to support various throughputs at different levels of power consumption. We have designed major internal blocks of MAP decoder using extensive steering logic to support radix-2/4/8 operating modes. These designs enable efficient clock-gating of our decoder for low-power consumption in different operating modes. This decoder-architecture is post-layout simulated in 65 nm-CMOS process and its performance analysis showed that the bit-error-rate (BER) of 10\(^{-4}\) could be achieved at 5 dB. Implementation result shows that the suggested MAP decoder could achieve throughput in the range 270−810 Mbps with the corresponding power consumption range of 12.24−37.67 mW. In comparison to the state-of-the-art, our design achieved 38% higher throughput and 61% lower power consumption.

The process of image acquisition, conversion of images into different form and transmission of images for various applications the originality of capture images are affected by different noises. The various techniques are proposed for removing noises in digital images. The main problem of these techniques is degrading the image information. Hence, in this paper, an efficient VLSI (Very Large Scale Integrated Circuits) implementation of Trimmed median filter algorithm with T-Model mask technique is used for removal of impulse noise is proposed. The proposed algorithm removes the noise presented in digital images without degrading the image information. The VLSI architecture implemented on FPGA (Field Programmable Gate Array) by pipelining with parallel processing in order to improve the performance of filtering process and reduces the delay. The performance of proposed algorithm is compared with different denoising methods and implemented on FPGA.

This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standard’s filter while designing a root-raised-cosine finite-impulse response filter for multistandard DUC for three different standards. In the next step, a 2-bit binary common subexpression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with 36% improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and can be considered more appropriate for designing the multistandard DUC.

This paper presents a new area and power efficient VLSI architecture for least-mean-square (LMS) adaptive filterusing distributed arithmetic (DA). Conventionally, DA basedLMS adaptive filter requires look-up tables (LUTs) for filteringand weight updating operations. The size of LUTs grows exponentially with filter order. The proposed scheme has reducedthe LUT size to half by storing the offset-binary-coding (OBC) combinations of filter weights and input samples. To make theadaptive filter more area and power efficient, it is not necessary todecompose LUT into two smaller LUTs. Hence, by using the nondecomposed LUT the proposed design achieves significant savingsin area and power over the best existing scheme. In addition, the proposed architecture involves comparatively lesser hardwarecomplexity for the same LUT-size. From synthesis results, it isfound that the proposed design with 32nd order filter offers 19.83% less area and consumes 20.54 % less power; utilizes 16.67 %and 19.04 % less number of LUT and FF respectively over thebest existing scheme.

Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition.

Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds) in real-time for standard PAL (720 × 576) size color video.

A new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the subexpression sharing technique that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI.

Lightweight cryptography plays an essential role for emerging authentication-based pervasive computing applications in resource-constrained environments. In this paper, we have proposed resource-efficient and high-performance VLSI architectures for PRESENT block cipher algorithm for the two key lengths 80-bit and 128-bit, namely PRESET-80 and PRESENT-128. The FPGA implementations of these architectures have been done on LUT-6 technology based Xilinx Virtex-5 XC5VFX70T-1-FF1136 FPGA device. These architectures have a latency of 33 clock cycles, run at a maximum clock frequency of 306.84 MHz and provide throughput of 595.08 Mbps. They have been compared with the two different established architectures. It has been observed that the PRESENT-80 architecture consumes 20.3% lesser FPGA slices and there is a gain of 25.4% in throughput. Similarly, the PRESENT-128 architecture requires 20.7% lesser FPGA slices alongwith a reduction in the latency by 27.7% and an overall increase of throughput by 69.1%.

The Ultra High Definition (UHD) broadcasting is being prepared to start globally. However, due to a huge amount of data compared with HD data, a processing them in real-time is very difficult. The editing of broadcasting is more difficult because it has to support multiple channels simultaneously. In this paper, we propose a dedicated Very Large Scale Integration (VLSI) to accelerate and control the simultaneous capture or playback of 4K UHD audio and video data from or to multiple channels. Finally, we implement hardware platform based on Field Programmable Gate Array (FPGA) to embed VLSI and integrate it with a UHD camera, a display and a server successfully.

In this paper, a new approach to design VLSI architecture for DSSS is proposed and implemented. In this we aimed towards designing a low power and low complexity architecture. An extremely lucid technique is implemented in Generating the Pseudo Random Sequence, which is the principal component in the design. The various blocks of the design like encoder, decoder, linear feedback shift register etc., are realized using low power VLSI components with an ease of low complexity approach. The Design is implemented on XA9536XL CPLD using XILINX ISE simulator and XILINX XST synthesizer. The results reveal that the power consumption, number of slice registers and other combinational circuits are less compared to the existing architectures.

In this paper, a design of high throughput VLSI architecture of MQ-Coder is proposed. Usually, because the regular operation of the MQ-Coder is sequential, the coding speed will be bottlenecked at the interface between the output of the Bit-Plane coding and the input of the MQ-Coder. Therefore, the proposed MQ-Coder architecture can process two symbols for each clock cycle. The main characteristics are the prediction of index, the simplified condition of renormalization, and the partly parallel architecture in renormalization. From synthesis results of the DC tools, using the TSMC 0.18 μm technology library, the frequency can reach 285.4MHz, which is comparable to that of other architectures and suitable for chip implementation.

High-performance algorithm and VLSI architecture for H.264/AVC context-adaptive, variable-length decoder (CAVLD) run_before computations are proposed to reduce the computation cycles. The run_before values of input symbols are estimated if they are zeroes in parallel. By skipping the estimation step when long symbols starting with ‘000’ are input, the architecture was drastically simplified while maintaining high performance. Experimental results showed that the performance for run_before computations improved by 68% on average when four symbols were estimated in parallel in comparison with sequential estimation of the symbols. The area of run_before is increased by 23% by the proposed architecture.

Data transmission of electroencephalography (EEG) signals over Wireless Body Area Network (WBAN) is currently a widely used system that comes together with challenges in terms of efficiency and effectivity. In this study, an effective Very-Large-Scale Integration (VLSI) circuit design of lossless EEG compression circuit is proposed to increase both efficiency and effectivity of EEG signal transmission over WBAN. The proposed design was realized based on a novel lossless compression algorithm which consists of an adaptive fuzzy predictor, a voting-based scheme and a tri-stage entropy encoder. The tri-stage entropy encoder is composed of a two-stage Huffman and Golomb-Rice encoders with static coding table using basic comparator and multiplexer components. A pipelining technique was incorporated to enhance the performance of the proposed design. The proposed design was fabricated using a 0.18 &mu, m CMOS technology containing 8405 gates with 2.58 mW simulated power consumption under an operating condition of 100 MHz clock speed. The CHB-MIT Scalp EEG Database was used to test the performance of the proposed technique in terms of compression rate which yielded an average value of 2.35 for 23 channels. Compared with previously proposed hardware-oriented lossless EEG compression designs, this work provided a 14.6% increase in compression rate with a 37.3% reduction in hardware cost while maintaining a low system complexity.

This paper presents a VLSI architecture of MMSE detection in a 4×4 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.

This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters. The novelty of this architecture is the possibility to compute the 5/3 wavelet results into the 9/7 data path with a reduced number of adders compared to other solutions. The multiplierless architecture has been characterized in terms of performance through simulations into a JPEG2000 environment and compared to other solutions. Implementation on a 0.13-mum standard cell technology shows that the proposed architecture compared to other multiplierless architectures requires a reduced amount of logic with excellent performance.

In this brief, a low-cost technique to implement variable-length coding (VLC) is presented. Instead of using a large codeword table as with most traditional methods, we employ two smaller tables, symbol-address table and section-based table, to encode input symbols. Compared with previous methods, our VLC implementation can reduce about 17% to 38% of memory space for storing larger VLC tables in MPEG-4 application. Synthesis results show that the proposed VLC encoder and decoder occupy 19761 and 20187 gate counts, respectively.

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 /spl mu/m CMOS technology and requires only 150 k gates for a total area of 1.5 mm/sup 2/ consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator.

A novel class of linear soft-input soft-output detectors featuring boosted communications performance is introduced. Compared to state-of-the-art linear detectors, the detector has an SNR gain of up to 2.4 dB. We shortly summarize the algorithm, and sketch a suitable architecture. The corresponding ASIC implementation shows the feasibility and efficiency of the concept. It achieves the IEEE 802.11n standard's peak data rate of 600 Mbit/s.

A methodology for the VLSI implementation of Cellular Automata (CA) algorithms using the VHSIC Hardware Description Language (VHDL) is proposed for the first time. This methodology builds a bridge between the CAs as models of physical systems and processes and the CAs as a VLSI architecture. A translation algorithm is developed that has as input the CA algorithms that simulate physical systems and processes, and as output the corresponding VHDL code. The parameters of this translation algorithm are defined by the user and can be automatically mapped into synthesizable VHDL. An example, where this methodology is applied to the hardware implementation of a CA algorithm for automated visual inspection, is presented.

Currently, considerable research is being performed on multiplierless structural methods for fixed coefficient filters, but not much research has been done on structural methods for creating adaptive filters whose coefficients vary with time. A few multiplierless structural methods have been proposed as structural methods using distributed arithmetic, but these conventional methods use particular encoding for input signals, and thus experience very high levels of degradation in their convergence characteristics. The authors improve significantly the convergence characteristics by generalizing this method using a new two's complement method. In addition, the authors propose a VLSI architecture not considered in conventional methods and perform VLSI evaluations of their structural method. The results show that the authors' proposed method can dramatically reduce power consumption and hardware requirements while sustaining high performance and very low latency compared to structural methods that use a multiplier. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 84(5): 1–12, 2001

This paper proposes a polynomial search (PS) algorithm and architecture to solve the motion estimation problem in video coding. Simulation results show that the proposed method is not only flexible, but also requires fewer computations to achieve the same mean absolute error results (for QCIF and sub-QCIF video) compared with the existing fast-search algorithms. Finally, a VLSI architecture is also developed to efficiently implement the PS algorithm.

A real-time algorithm and its VLSI implementation for edge linking is presented. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n+12 clock cycles, where n is the number of pixel columns in the image.

Using spurious power suppression technique (SPST) in VLSI will reduce the power consumption of the system significantly. Here we are going to implement this design in Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter architecture. When we are using this technique in this multipliers the no of partial products generated will be reduced to half which reduces the computation. Then obviously the power consumption is also reduced by this method using the various hardware device.

An Eigenvalue-based detection (EBD) scheme, is proposed as an efficient method to overcome the noise uncertainty and the SNR wall problem in conventional energy detection (ED) schemes. Despite remarkable efforts made to analyze the EBD performance, a VLSI implementation is missing in literature. In this paper, a new FFT-based EBD algorithm is introduced, which eliminates the need for filter banks and discrete wavelet packet transform to channelize the input signal. The proposed method enables the utilization of the EBD algorithm in high-resolution spectrum sensing approaches. Moreover, it enables the detection of signals with SNRs as low as -10 dB. A low-power, area-efficient yet real-time VLSI architecture is developed for the algorithm, which is implemented in a 0.18μm CMOS technology. The implemented design occupies a total area of 3.4mm2 and dissipates 78mW for a 40 MHz sensing bandwidth consisting of 32 sub-channels.

This paper presents a hardware-efficient and high-throughput quantization implementation for H.264/AVC high profiles encoder. The constant multiplication in quantization is accomplished by time-multiplexed multiple-constant multipliers (MUX-MCM). By rational pipeline decision, the proposed design manages to achieve a high throughput at a low area cost. Synthesized with SMIC0.18µm technology, the proposed design reaches a maximum operating frequency of 250Mhz with a throughput of 1Gpixels/sec at the hardware cost of 28.56 Kgates.

Intra prediction with fine directions is a critical feature in the new High Efficiency Video Coding (HEVC) standard because it provides significant performance gain. Different from the intra prediction in the H.264/AVC, this approach is more complicated in terms of computation and memory access, which makes the VLSI design very difficult. In this paper, we propose an efficient uniform architecture for all of the 4×4 intra directional modes. The architecture is implemented by a register array and a flexible reference sample selection technique. This novel architecture does not need to project the samples from the side reference to the main reference. Thus, it reduces the processing latency and the number of registers considerably. The proposed architecture has been implemented with TSMC 0.13μm CMOS technology. Simulation results show that the proposed architecture only needs 9020 logic gates for 17 directional modes and can run at 150 MHz operation frequency.

This paper is about the real-time implementation of a speech recognition system for Spanish. A VLSI architecture, for implementing the Viterbi Algorithm, is employed in order to provide it with the necessary processing speed.

We present a fast and low-cost fractional motion estimation (FME) and its corresponding VLSI architecture for H.264/AVC. The proposed direction-based FME algorithm just searches 8 points and employs four hadamard transforms to reduce computation time and hardware cost. Additionally, we propose two mode reduction methods to skip most search modes to further reduce computation complexity. Our FME can code a macroblock within 631 cycles on average and quite enough to achieve real-time coding for HD1080p video sequences operating at the frequency of 155 MHz.

To improve the coding gain, many fractional motion estimation engines contain processing units for calculating the sum of absolute hadamard-transformed differences, which take about half of the overall area. In this paper, a new cost of the “Sum of Absolute Half-Transformed Differences” is proposed for H.264/AVC. The VLSI architecture of the new processing unit saves about 50% of the area with a very slight loss of the coding gain. Besides, an efficient all-zero block detection method could be easily implemented in this architecture, which can detect about 80% more all-zero blocks compared to the traditional approaches.

This paper presents a reliability-configurable coarse-grained reconfigurable array for signal processing, which offers flexible reliability to soft error. A notion of cluster is introduced as a basic element of the proposed reconfigurable array, each of which can select one of four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by a cluster of the reconfigurable array. A fault-tolerance evaluation of Viterbi decoder mapped on the proposed reconfigurable array demonstrates that there is a considerable trade-off between reliability and area overhead.

Motion compensation is the most critical part for the performance of H.264 decoder. Through fully analysis of the interpolation algorithm, a symmetry characteristic in the algorithm has drawn our attention. Based on a precise deduction, a new VLSI architecture for motion compensation lum interpolation is presented in this paper. This architecture is based on separated 1-D approach and reuses the horizontal half-sample interpolation 6-tap FIRs and the horizontal vertical half-sample interpolation 6-tap FIRs. Experiment results shows that compared with arithmetic adopting separated 1-D approach referenced, the proposed arithmetic can save 5 6-tap FIRs and 6 eight-bit registers. A H.264 decoder adopting the proposed approch can achieve real-time decoding 30 fps baseline H.264/AVC video with 1080HD resolutions at a clock speed of 100MHz1.

in this paper, a new flexible VLSI architecture of H.264/AVC decoder is presented. The proposed design implementation can get a good performance result as fully pipelined construction.

The current trend of hardware intensive signal processing is based on the CORDIC. Over the years many architectures have been proposed to address issues pertaining to throughput and latency. In this paper, we are proposing a pipelined architecture for the VLSI implementation of radix-4 CORDIC rotator with redundant arithmetic to achieve low latency compared to the available architectures.

This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited. Publisher's Version WOS:000258990400184

In the Letter ‘Unified VLSI architecture for photo core transform used in JPEG XR’, the authors proposed a hardware architecture to implement the three elementary 2 × 2 transform operations for the photo core transform used in JPEG XR. However, there are some errors in their implementation, dataflow and reported resources used. In this Letter, we point out those errors and suggest the corresponding corrections. We also provide constant additions which must be added to the results of the implementation to conform the standard.

We present an O(log n) compare-exchange time parallel algorithm to compute the connected components of a given graph. We also introduce a simple regular VLSI architecture on which the proposed algorithm can readily be implemented requiring n3 identical processing elements and O(n) communication time, where n is the number of vertices in the graph.

This paper proposes a cost-effective VLSI architecture to improve the three-step search (TSS) algorithm for efficient motion estimation. A weighted SAD is defined as the new distortion measure instead of SAD for motion vector selection to remedy the fault of the TSS algorithm. The proposed TSS architecture is superior to conventional TSS architecture in terms of coding performance. Moreover, the additional hardware implementation cost of the proposed architecture is relatively negligible. The proposed architecture achieves best tradeoff in terms of speed and hardware cost.

Hybrid transform and scalar quantization is a key component in ITU-T H.264, and mathematic analysis and decomposition are elaborately made for its hardware implementation, the calculation process is simplified, all time-consuming and hardware expensive multiplication and division are avoided effectively. A new block parallel VLSI architecture mainly containing a 2D direct hybrid transform engine and a full wiring 52-level scalar quantizer is proposed. It is very suitable for pipeline acceleration, and the block throughput rate can reach 156 M/s with one register row inserted, which can satisfy 4096times2304@150 Hz digital video coding in real-time easily, even all macroblocks are predicted with intra_16times16 mode.

A vector quantization (VQ) algorithm based on rotating compressed codebook is proposed. Compare with the typical vector quantization algorithm, the algorithm decreases 75% memory size and 75% input codebook bandwidth. The VLSI architecture for the algorithm was designed, and parallel pipeline was employed in the critical unit. The architecture was verified in FPGA, operation rate of the whole system can achieve 87.35 MHz. It can support real time application of 512times512 at 30 fps when the operation rate is 55 MHz.

A novel CSI-aided demapping method for dual-carrier modulation (DCM) is proposed for multiband-OFDM systems. The proposed method utilizes the channel state information (CSI) to calculate the soft decision values, which are given by the approximate log-likelihood ratio (LLR). In this paper, it is shown that the soft decision values are given as the differences between two squared Euclidean distances. By reducing the noise-amplifying effect, the proposed method improves the error performance of conventional methods, by a signal-to-noise-ratio (SNR) of 3dB in the presence of channel estimation error and quantization noise. The VLSI architecture suitable for this method is also proposed, verifying that the performance gain comes with a slight increase of hardware complexity.

This paper presents a practical implementation of a layered space-time (LST) receiver targeting a Xilinx Virtex-II FPGA. The architecture is based on multipass burst processing, and includes burst buffers for each antenna, channel parameter estimation modules exploiting a training sequence, and a simple matrix inversion adaptation mechanism. LST architectures involve significant implementation complexity and various refinements have been proposed in the literature to mitigate this aspect. Our receiver is based on novel modifications to the standard LST algorithm which enable unprecedented implementation simplicity, avoiding complex operations such as divisions and square roots, while suffering a negligible BER degradation.

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data-reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requirements of the decoder when compared to the state-of-the-art LDPC decoders. The ASIC implementation of the proposed fully parallel architecture achieves throughput of 4.6 Gbps (for a maximum of 15 iterations). The chip size is 2.3 mm times 2.3 mm in 0.13 micron technology

A pilot based EM channel estimator is proposed. The channels are estimated using the EM (expectation-maximization) algorithm, while making use of pilot tones to obtain the initial estimate for iterative steps. Simulation results show that the bit error rate (BER) can be significantly reduced compared with conventional algorithm and iterative times are less than the common EM algorithm. VLSI architecture for the algorithm is proposed