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We have proposed "PN-Body Tied SOI FET (PNBT-FET)" as a candidate of steep subthreshold slope (SS) devices, such as tunnel FETs and negative capacitance FETs, which will be a key device for expanding ultralow power IoT applications. We have already reported that PNBT-FET has SS below 1mV/dec over several orders of the drain current even with ultralow drain voltage of 0.1V [1] – [2] . We also reported the drain current (Id) enhancement effect on PNBT-FET, at previous IEEE SNW [3] .

We investigated the mechanism of the PN-body tied (PNBT) silicon on insulator (SOI) field effect transistor (FET) with a 65 nm thin buried oxide (Box) FD-SOI technology. We clarified the mechanism by which the 65 nm PNBT-SOI-FET shows steep subthreshold slope (SS) only with negative or positive substrate bias (V sub ). We compared this behavior with a 200nm SOI-FET technology, which needs no V sub to exhibit steep SS. It coincides with our first measured confirmation of the steep SS on the 65 nm SOI technology. The hole accumulation in channel by the V sub and also the gate voltage is a key for the 65 nm PNBT SOI-FET because the 65 nm SOI-FET is a more fully depleted SOI. The specific shift of the steep SS voltage was also analyzed.

In this paper, the diode characteristics of our newly proposed super-steep subthreshold slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.

We have proposed the super steep subthreshold slope (SS) “PN-Body-Tied SOI-FET (PNBTFET)”. It shows the perfect DC characteristics as a steep SS device, which is one of hot topics on the current research of Si devices. It shows SS < mV/Dec over 5 decades of the drain current with an ultralow drain voltage down to 0.1V. The steep SS on N-channel and also on the P-channel PNBT-FET have already been demonstrated. The CMOS with PNBT-FETs will open LSI with the ultralow power supply voltage around 0.1V, which is promising for the ultralow power IoT edge systems. The ultralow voltage rectification of the 10mV amplitude has also been confirmed with the MOS diode of the PNBT-FET. It is also promising for high efficiency rectification on RF energy harvesting. The research status on the PNBT-FET is reviewed as well.

Rectification of the ultralow voltage signal, up to 10mV, was experimentally confirmed, for the first time, by our new device of the super steep subthreshold slope “PN-body Tied SOI-FET” (PNBT-FET). It comes from the surprisingly sharp turn-on characteristics of PNBT-FET, even with measuring on the ultra small voltage range. It is impossible with the conventional diodes, due to becoming the tangential line. Rectification up to 30 MHz was also confirmed with PNBT-FET. It is a good news for PNBT-FET because its conduction mechanism has the low speed concern. Those rectification demonstrations will be promising for small voltage rectification on RF energy harvesting and ultralow voltage sensing applications.

We demonstrated a P-channel super steep Subthreshold Slope (SS) PN-Body Tied (PNBT) SOI FET, for the first time. We found out that the substrate bias is necessary for the appearance of the super steep SS on the P-channel PNBT. The device shows a super steep SS (

We have proposed a super steep Subthreshold Slope (SS) “PN-Body Tied SOI-FET”. It shows the super steep SS (∼ 35 μ V/dec) over 3 to 5 decades of the drain current with an ultra-low drain voltage down to 0.1V. We have also improved it to reduce the operating body voltage below 1V and have clarified that the floating body effect of the SOI is a key mechanism for appearance of a super steep SS. The research status on the device was reviewed, here.

Gate controlled diode (GCD) characteristics with our newly proposed super steep subthreshold slope (SS) “PN-Body Tied SOI-FET” was shown, for the first time, compared with the conventional diodes. It shows the super steep characteristics, the low leakage current and the sharp On-characteristics even on the ultralow voltage range of 50mV. The simple circuit simulations also indicated that the GCD with “PN-Body Tied SOI-FET” will achieve the high efficiency rectification on the ultralow input power of the RF energy harvesting. Additionally, the slight shift of the voltage of the zero current was confirmed as a specific characteristics on this GCD.

It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFET's which show the super steep SS with the ultralow drain voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N−. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.

We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (

Gate controlled diodes (GCD) and rectifiers using the GCD with the different threshold voltage (Vt) of the MOS by the ion-implantation were fabricated with 0.18um CMOS technology. The DC characterization of the GCD revealed that the turn on voltage of the GCD is reduced and becomes lower than the Schottky Barrier Diode (SBD) when the Vt of the MOS is reduced and there exist the bulk leakage pass of the MOS on the reverse leakage current of the 0.18um GCD. It was also clarified that the parasitic capacitance of the GCD will be lower than the SBD. From simulations and measurements of the rectifier, it was found out for the first time that the rectification efficiency of the rectifier using the GCD has a peak value when changing the Vt of MOS in the GCD, and the rectification efficiency of the rectifier using the GCD with the near zero Vt of the MOS overcomes the rectifier' using the specially designed SBD for the small signal applications, on the ultralow power input of the RF energy harvesting.

Ultra Low Power (ULP) LSI's require the steep subthreshold slope (SS) MOSFET. However, the theoretical SS limit of the conventional MOSFET is 60mV/dec at the room temperature. Recently, devices which have the less than 60mV/dec SS, such as the Tunnel FET (TFET) and the Impact Ionization MOS (I-MOS), have been studied. In addition to those, the steep SS MOSFET's using the Floating-Body (FB) SOI have been proposed. In this work, we report our finding of the FB and the Body-Tied (BT) SOI MOSFET with the super steep SS (

Super steep subthreshold slope characteristics in the FB and the BT are investigated with TCAD. The mechanism of the enhanced DIBL and the addition of the positive feedback PBT action by the forward biased emitter-base voltage are proposed to explain the difference between the FB and the BT.

The TiSi2 local wiring technology has been newly characterized from the viewpoints of dopant interdiffusion and power reduction. It was found that only the p+/n junction degrades when TiSi2 local wiring connects the n+ layer and p+ layer. The results of electrical measurements using a set of new test patterns suggest the reason to be that boron does not diffuse from TiSi2 to Si due to the high efficiency of TiB formation. More than a 20% reduction in power dissipation at a low-power supply voltage of 1 V was obtained, which demonstrates that the scheme is promising for low-power sub-half-micron complementary metal oxide semiconductor.