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Current Transformers (CTs) saturation leads to distortion of current waveform and operational malfunction of protection relays. This paper introduces a practical and simple method to prevent CTs saturation. The method uses a negative voltage feedback and applies it to CT secondary side. The injected voltage opposes the excitation voltage of CT in a manner that the magnetic flux of CT remains almost constant under saturation level for any faults. The method is categorized as a hardware solution, does not need to detect the CT saturation time and works either for digital or non-digital relays. The method is verified in a wide range of simulations and experimental results. The obtained results show that the method is reliable, effective, and accurate.

This paper focuses on the operation of hybrid modular multilevel converter and proposes an effective approach that guarantees the full performance of the converter even in post-fault condition. The main novelty of this paper is utilizing negative arm voltage levels in a way to compensate the missed voltage. After the fault occurrence, the DC component of the arm voltages as well as the DC-link voltage are adjusted based on the fault states to restore the nominal balanced line-to-line voltage in the post-fault condition. In comparison with the previous methods, the proposed method does not add any hardware to the circuit to restore the nominal output voltage. The capacitor voltage of submodules, also, does not increase after fault occurrence. Therefore, the converter can maintain its nominal line-to-line voltage in post-fault condition without extra implementation costs or overdesign requirements. To validate the effectiveness of the proposed method, detailed simulation and experimental results are provided.

In this article the initiation of a corona discharge from a negatively charged point with a small radius of curvature is investigated experimentally and as a result of modeling. Modeling showed that the periodicity of the discharge current in our model is observed only in the case of adding electron detachment reactions to the plasma-chemical scheme. The reason for the pulse-periodic mode of current flow is the presence of negative O2− ions. It was shown experimentally that the first streamers at a minimum voltage have a ball shape.

SiC MOSFETs are well known for possessing lower losses compared with silicon MOSFETS or IGBTs. In order to drive them efficiently, suitable drivers must be designed. However, most commercially available drivers and drivers in literature are suitable for only a limited range of SiC MOSFETs due to limitations on the MOSFET's gate voltage ratings. Hence, the drivers do not allow the designer to easily experiment with different SiC MOSFET models. In this paper, a generic SiC gate driver with adjustable positive and negative voltage rail is presented. The performance of the proposed driver is compared with a commercially available driver through experiment and it is shown that the proposed gate driver is able to drive the chosen SiC MOSFET more efficiently. Accepted version

DC-DC converters are commonly used in power-conserving applications, like battery-operated equipment to regulate to a lower voltage, boost an input voltage or invert it to create a negative voltage. Efficiency is an important DC-DC converter characteristic as it may achieve efficiencies greater than 95% under optimum conditions. However, this efficiency is limited by dissipative losses in the components.

The Resistive-Capacitive (RC) model has been widely adopted for analysis of the electric field in oil-pressboard insulation under DC voltage. However, studies in this regard have indicated that the charge polarity effect in oil-pressboard insulation, namely the stronger adsorption of negative charges by pressboard, could not be adequately captured by the RC model. In order to analyze the electric field with due consideration of charge polarity effect, the present paper adopted the Kerr electro-optic techniques to have measured the electric field in the oil spacing under DC voltage for two experiments models with Model I having two oil spacing divided by a pressboard at the spacing ratio of 1:1, and the Model II at the spacing ratio of 1:2. As Model I is concerned, the strength of electric field in the upper oil spacing reached 1.61 times of the initial one under positive voltage and 1.60 times under negative voltage, while the field in the lower oil spacing registered as one eighth of the initial one under both positive and negative voltages. For Model II, the electric field strength in the upper oil spacing reached 2.3 times of the initial field under positive voltage and one fourth of that under negative voltage, showing much stronger charge polarity effect compared to that in Model I. In order to analyze the effect of interface charge on electric field, an electric field analysis model based on interface charge, named Interface Charge Polarity Effect (ICPE) Model, is proposed in this paper. Referring to the different adhesive abilities of positive and negative charges on pressboard, the influence of interface charge on electric field can be analyzed by the proposed model, which could make the contribution to the insulating design and proofread for the converter transformer.

The influence of electrodes on unipolar switching characteristics of a Pt/HfO2/Pt resistor with symmetric electrodes is investigated by comparing the reset voltage ( $V_{R})$ , set voltage ( $V_{S})$ , current at low resistance state ( $I_{\mathrm{ LRS}}$ ) and high resistance state ( $I_{\mathrm{ HRS}})$ , and $I_{\mathrm{ LRS}}/I_{\mathrm{ HRS}}$ with positive and negative voltage polarities. The values of $\pm V_{R}$ and $\pm V_{S}$ of the Pt/HfO2/Pt resistor for respective positive and negative polarities are very similarly distributed. Concerning current levels at two resistance states ( $I_{\mathrm{ LRS}}$ and $I_{\mathrm{ HRS}}$ ), however, unexpected asymmetric current characteristics of the Pt/HfO2/Pt symmetric resistor are observed. The asymmetric current behavior at the symmetric Pt/HfO2/Pt resistor indicates the role of different environments at top and bottom interfaces, although they are formed with the same electrode material using the same deposition method. Two types of interfaces, Pt/HfO2 and HfO2/Pt, are analyzed using X-ray photoelectron spectroscopy. The bottom interface of HfO2/Pt, postprocessed with insulating HfO2 film deposition, is probed nonstoichiometric HfO x and weak oxidation of Pt electrode and is influenced by the variation of the current levels and the current ratio at both high and low resistance states.

We studied the effect of bias voltage between slider and disk surfaces to reduce lubricant pickup by the slider. A perfluoropolyether (PFPE) lubricant film, which is coated on the disk surface, has been considered to be charged to a negative voltage by the airflow on the rotational disk surface. Because the PFPE lubricant film is negatively charged, the lubricant pickup should be reduced by a bias voltage with a negative voltage on the slider surface. We confirmed changes in the lubricant pickup in a lubricant pickup test conducted at different bias voltages. A positive voltage of the slider accelerated the lubricant pickup, whereas a negative voltage reduced it.

In this paper, a novel coordinated control method is proposed to handle the negative voltage impacts on weak sub-transmission systems, which are caused by wind power fluctuations. Firstly, wind variations are divided into large and small fluctuations. Then, according to the different control characteristics of on-load tap changers (OLTCs) and static compensators (STATCOMs), the OLTCs are used to minimize the impacts caused by large fluctuations, while the STATCOMs are used to eliminate the impacts introduced by small fluctuations. The model predictive control (MPC) and a consensus based distributed control techniques are adopted to design the control schedules of OLTCs and STATCOMs, respectively. It is shown that by the coordination of OLTCs and STATCOMs, voltage violations of points of interconnection (POIs) are eliminated, and voltage fluctuations at unregulated load buses are mitigated. The effectiveness of our proposed control scheme is presented through a case study on the modified IEEE 14-bus test system with a real wind power profile. According to the simulation results, it turns out that the proposed approach can reduce the operation number of OLTCs significantly, and decrease the required capacity of STATCOMs dramatically by comparison with the existing control scheme.

This paper proposes a novel circuit model of the 1.2/50-8/20μs combination wave generator (surge wave generator). The novel model solves the problem that the 1.2/50–8/20μs combination wave generator in IEC 61000-4-5 standard cannot produce the negative open-circuit voltage waveform. By formula derivation and calculation, it is proved that the standard model is unable to produce negative voltage waveform while the novel model can. Meanwhile, the waveform curve produced by the novel circuit model can be adjusted in larger range. Also, it can be quicker to adjust compared with the standard model. Furthermore, the novel model can modeling the actual surge more accurately.

Due to the electrical and physical analyses, the robust negative voltage unipolar resistive switching behaviors in Ti/ZrO2/Ti/ZrO2/Pt device have been investigated. The Ti diffusion in ZrO2 film can generate more amounts of oxygen vacancies in it, which leads the lower value and narrower variation in forming voltage. Moreover, the good performances with more than 1000 switching cycles and long retention test can be achieved in the present device.

Radio interference (RI) of DC transmission lines due to the corona discharge has become a restraining factor of power grids design and operation, so the suppression of RI is very important. In this paper, a new idea for suppressing RI by mounting ferrite cores on the conductor is proposed. By measuring and comparing RI values of the test stranded wire with and without ferrite cores, test results show this approach to suppress RI is effective. Further research results also show inhibitory effects at negative voltage are better than positive voltage and the material of ferrite cores affects the inhibition effects.

The display quality improvement of electrophoretic paper largely depends on the increase in the number of grayscale, but it will make drive mode design complicated. The inhibition of residual driving voltage also becomes more difficult. This paper presents a new 16 gray-scale driving schema based on the DC-balance principle, improve the display quality of electrophoretic display (EPD). The display process is divided into DC rebalance phase and gray-scale drive phase. For every gray-scale conversion, pixel units make the original gray scale reach the basic gray scale via extreme white stage in the DC rebalance phase. Then a new gray-scale image is driven to show in the gray-scale driving phase. During the two sequential gray-scale conversions, voltages in the drive phase of the ith conversion and DC rebalance phase of the (i+1)th conversion always maintain DC balance, namely overall time of applying positive voltage in these two phases is equal to the overall time of applying negative voltage. The experimental results show that the proposed approach can effectively avoid the damage of driving electrode and display medium caused by the residual voltage accumulation, thus significantly extend the service life of the display.

In this paper, a memristor with structure of Ag/ PEDOT:PSS/ Ta was fabricated and measured at room temperature. The conductance of the device decreased continuously as the consecutive negative voltage scanning. But for positive voltage sweeping, the conductance value reduced initially then increased, which was quite different from previous reported experimental results. The relaxation phenomenon was observed under the consecutive voltage pulses, which can be used to achieve a synaptic learning behavior. It is found that the PEDOT:PSS layer was critical for the special characteristics.

Resistive switching (RS) behavior of Bi25FeO40:PCBM nanocomposite thin films have been studied by using a FTO/Bi25FeO40:PCBM/Ag device structure. The device switches from high resistance state (HRS, “0”) to low resistance state (LRS, “1”) and from LRS to HRS at small applied voltages in the positive and negative voltage sweeps respectively which confirms the RS behavior of the fabricated device. The fabricated device shows good retention characteristics for long time (> 103 sec) at read voltage ± 0.5V. The forming free bipolar RS have been observed with ratio of resistance in HRS and LRS i.e. RHRS/RLRS is higher (∼ 87) at read voltage − 0.5V compared to that of at read voltage + 0.5V (RHRS/RLRS ∼10). Resistance ratio and good retention performance confirms the non-volatile RS behavior of the device and makes the device a suitable candidate for next generation resistive random access memory (ReRAM) devices.

The tunable properties of Pt/PMN-PT/LSCO/Ir capacitor have been studied under different applied voltages and frequencies. The PMN-PT thin film exhibited good dielectric tunability. A tunability of 70.3% at 12 V and 100 kHz is obtained for the film under negative voltage bias. For the positive voltage bias, the tunability is 68.7% which is smaller than the value under negative voltage bias. The asymmetric distribution of charged defects is suggested as possible causes of the asymmetric capacitance–voltage (C–V) behaviors of ferroelectric capacitors. On the other hand, the frequency dependency of the capacitance's tunability indicated that the interface has strong influence on the frequency stable of tunability.

New a-Si:H TFT gate driver circuit (ASG) for low power consumption is proposed and fabricated. For the first time, the proposed ASG can set TFT turn off voltage to the negative voltage rather than zero voltage that the conventional one uses, therefore, TFT leakage current can dramatically be reduced by 1/100. The size of TFT in new ASG, which discharges the leakage current, can be reduced so that the power consumption of new ASG is 43% of the conventional one.

The effects of a transient external voltage application on the bioanode performance of microbial fuel cells (MFCs) inoculated with mixed cultures were investigated. Different positive and negative external voltages were applied to a set of bioanodes. The MFCs under +1, −1, and −5 V voltage applications achieved higher current densities than the control during the start-up period. The MFC exposed to a voltage of +1 V had the highest maximum power density of 73.5 mW m−2 after a 96-h operation. However, the +5 and +10 V voltage applications delayed or even deteriorated the MFC start-up. The −10 V voltage application initially induced a higher power output, but later had a detrimental effect on the MFC performance. The negative voltage application was proven to enhance the catalytic activity of the bioanode, and found to be partially responsible for the improved MFC bioanode performance.

The effect of constant negative voltage stress on charge trapping and interface states of Al/HfO 2 /SiO x N y /Si structures are investigated. The reduction in the capacitance of C – t characteristics and a significant shift in C – V curves towards negative voltage axis reveal that the charge trapping/detrapping occurs at the Si/SiO x N y /HfO 2 interface and HfO 2 bulk. However, there is a relative increase in gate leakage current as a function of the voltage stress and time, owing to the trap-assisted tunnelling. It is suggested that these traps are probably Hf–OH neutral centers, originating from the breaking of bridging Si–OH and Si–NH bonds by mobile H + protons. This has potential application in non-volatile CMOS memory devices.

The wall-charge behaviors of the conventional and two types of single-sustain waveforms during address and sustain periods are investigated based on a simulated result and a Vt close-curve analysis. The single-sustain waveform means that the sustain pulse having both positive and negative voltage levels is applied only to the single-side electrode, i.e., the scan (Y) electrode in this paper, where the common (X) electrode remains grounded. In the single-sustain waveform, the address discharge characteristics were observed to be improved by applying a higher voltage level without causing a misfiring discharge during an address period. An asymmetric IR emission was observed for both positive and negative sustain pulses during a sustain period, which was caused by the simultaneous discharge, including the plate gap discharge between the scan (Y) and the address (A) electrodes only when applying the negative sustain pulse to the scan (Y) electrode.

In this paper, a new write assist technique is proposed to improve the write characteristics of 1T-1MTJ STT-RAM bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write ‘1’ operation. The proposed technique is compared with the best previously proposed techniques. The simulation results using 65nm CMOS technology show that the proposed write assist technique results in 19% improvement in write energy compared to the boosted wordline technique. In addition, the proposed write assist technique leads to 12% and 48% reduction in the access transistor width compared with boosted wordline and balanced write techniques, respectively. Furthermore, the maximum voltage across the MTJ is reduced by 20% and 6% compared with boosted wordline and balanced write techniques, respectively.

We have performed four-terminal measurements on a split-gate device with three overlaying finger gates. In our system, a one-dimensional (1D) ballistic constriction can be formed by applying a negative voltage on the split-gate. By changing the finger gate voltage, we are able to modulate the potential profile within the 1D constriction. In such a 1D ballistic structure we have observed that the conductance steps show a gradual decrease from 2 e 2 / h to 0.97×2 e 2 / h with increasing negative finger gate voltage. We suggest this phenomenon is due to different shifts of 1D subbands with changing spilt-gate voltage. Both simple analytical estimate for an adiabatic constriction and realistic modeling of the device give the same magnitude of the conductance decrease as observed in our experiments.

The possibility of generation of high-voltage pulses in the self-oscillation mode of a beam-plasma discharge is shown. Negative voltage pulses with amplitudes of up to 40 kV are recorded at the plasma facing electrode at a constant negative bias voltage of 200–300 V.

Inner-structural changes of a Cu/MoOx ReRAM was observed by in-situ TEM during the resistive switching. We succeeded for the first time to observe the structure changes in the continuous multiple resistive switching cycles. Cu-rich filament was formed in the MoOx layer during the SET process with positive voltage to the Cu electrode, and disappeared by negative voltage in the RESET process. It was also confirmed that thick filaments were generated when the current compliance for the SET process was increased. The most meaningful phenomenon is that the position of the filament changed at each SET process.

Properties of the ion sheath expansion in plasma are investigated for a target voltage with a finite rise time. A theoretical model for ion sheath expansion is developed when the negative target voltage increases linearly. The theory predicts that the sheath expansion is proportional to the square root of time at the beginning and is proportional to the 56 power of time later on. An experimental measurement has been carried out and the measured data are compared with theoretical results. It is shown that the sheath front propagates very fast at the beginning and slows down later, even for continuously rising negative voltage on target.

Etching of hydrogenated amorphous carbon (a-C:H) films in 0.1 M nitric acid was evaluated using surface plasmon resonance at the applied voltages of 0.0, −1.0, and 1.0 V. The etching rates of the a-C:H films as functions of the applied voltages and etching duration were obtained to be 0.0368 (at 0.0 V), 0.0117 (at −1.0 V), and 0.0074 nm/min (at 1.0 V). These results clearly indicate that the etching rates decrease significantly under the conditions of applying positive or negative voltage, demonstrating the enhanced corrosion resistance of the a-C:H films upon applying voltage.

High speed CCD cameras, current measured devices and impulse voltage divider were utilized to investigate the characteristics of rod-rod discharges. The discharge experiments in a 3m rod-rod gap were carried out under positive and negative switching impulse voltage. The characteristics of leaders propagation stimulated by positive voltage were compared with that stimulated by negative voltage. Although with certain similarities, the leaders which energized by different polarity voltage share differences such as the varied process of leader with the time, the length of upward leader, the proportion of upward leader, and the velocity of upward leader. These works have revealed the discharge process of rod-rod air gap more clearly, and are benefit for the study on the discharge mechanisms of the rod-rod discharges.

We present a theoretical investigation on the transport properties of the nanostructures consisting of magnetic-electric barriers produced by the deposition, on the top of a heterostructure, of metallic ferromagnetic stripe with an applied voltage. Both the transmission probability and the conductance are found to be greatly dependent upon the applied voltage. When a positive voltage is applied to the stripe, both the transmission probability and the conductance shift towards low-energy region and increase. Conversely, they move towards high-energy direction and reduce for an applied negative voltage.

We report that local modification and its erasing with a nanometer-scale size can be performed at a Au/Si(111) interface using ballistic electron emission microscopy (BEEM). By applying a negative voltage on the tip, a region was created where no BEEM current flows at the interface and was imaged with BEEM. The modified area can be erased by applying a voltage with the opposite polarity. It is found that the minimum size of writing and erasing corresponds to Au grains, suggesting a method of rewritable memory on a nanometer-scale dimension.

Experiences from the use of a measuring system for detection of partial discharges (PDs) at a repetitive, unipolar, square-like voltage with a rise time of 2.0 mus, are here presented. PDs were detected during the major part of the voltage flanks, even when the duty cycle of the applied voltage was not completely stable. The voltage was applied for relatively long time and one PD appeared at each voltage flank. As the measurement progressed however, the time intervals within which the PDs appeared shifted. This indicates that comparisons of results from measurements performed at e.g. different rise times or voltage levels can be difficult, due to the inherent stochastic variations in the PD appearance. One example of a time interval where the PDs at the negative voltage flank all appeared during the falling part of the voltage is also shown. Under such circumstances, it is important to be able to measure the PDs also during the voltage flanks to avoid that the test object is considered to be PD free.

The effect of applied DC voltage on the friction and wear of CNx sliding against stainless steel pin in air was clarified. Friction coefficient decreased with the increasing negative voltage to apply to the ball and disk in air. On the other hand, positive voltage increased friction coefficient. Friction coefficient of CNx in air decreased from 0.22 to 0.05 by applying electric voltage of DC −200 V. Specific wear rate was decreased with the increasing applied positive and negative voltage. It was considered that the oxidation of CNx was controlled by electric field.Copyright © 2005 by ASME

This paper presents the results of the effect of NO and N/sub 2/O annealing on the electrical characteristics of SiO/sub 2/ grown on the Si-faced n- and p-type 6H SiC by rapid thermal processing (RTP). For n-type 6H-SiC, the as-grown SiO/sub 2/ in pure O/sub 2/ gives near ideal C-V curves. NO annealing has little effect on the C-V curves while N/sub 2/O annealing makes the C-V curves shift to the positive voltage. For p-type 6H-SiC, NO annealing improves the C-V curves greatly. But N/sub 2/O annealing shifts the C-V curves to the negative voltage. Conductance measurements show that NO annealing decreases the interface state density for both n- and p-type 6H-SiC. N/sub 2/O annealing increases the interface state density for n-type 6H-SiC.

A novel BI-EPROM structure, which has a vertical PNP bipolar transistor in the drain of the conventional EPROM cell, is proposed for future low-voltage and high-speed nonvolatile memories. In the read operation, the large cell current is obtained by the embedded bipolar function. Moreover, since its drain is made of an N-base, it has a high immunity against the soft-write phenomenon and can tolerate a higher channel current. It can be programmed by applying high voltages to both the source and the gate, while the drain is biased 0 V or negative voltage. Its feasibility is confirmed by a test vehicle with a 0.8 mu m technology. >

In this paper, we report a multilevel unipolar resistive switching (RS) phenomenon with negative differential resistance (NDR) effect in Ag/SiO2/Pt sandwich structure. After positive electroforming process with low compliance current (ICC, 10 nA), a conductive filament consisting of isolated Ag nanocrystals is formed inside SiO2 layer. Then, an abnormal unipolar resistive switching (RESET voltage is larger than SET voltage) with NDR effect is obtained under negative voltage sweep without ICC. Based on I-V fitting and temperature dependence of the resistance results, we suggest that the abnormal unipolar RS is dominated by the charging/discharging of carriers in Ag nanocrystals. In addition, we demonstrate that the unipolar RS exhibits good performances, including large Roff/Ron ratio, high uniformity, long retention time, and multilevel storage potential.

Impulse voltage flashover of a 4 cm point-plane air gap was investigated. The positive-voltage flashover track was found to wander further away from the axis than that for negative voltage. A space-charge model is proposed to explain the difference between these trajectories.

Nanocluster memories are promising for future non-volatile memory applications. In this work thin SiO2 films were implanted with Ge+ and Si+ and annealed subsequently. Charge storage effects of the MOS capacitors have been studied through I-V and high frequency C-V measurements. Positive voltage pulses lead to a positive flatband voltage shift of the C-V curve. Detrapping by applying negative voltage pulses leads to a negative shift. The achieved programming window using 6 V / 100 ms pulses for Ge based structures is higher than that for Si (2.0 V vs. 0.2 V). However the retention times for Si based memories are longer. For dedicated process parameters microstructural investigations (RBS, XTEM) of Ge+ implanted SiO2 layers showed two bands of clusters, one near the interface SiO2/Si and one in the center of the SiO2 layer.

The dynamics of an atmospheric-pressure plasma plume generated in a controlled gas environment are studied. It is found that, at a particular pulse width, two or three plasma bullets are generated in each voltage pulse for both positive and negative voltage pulses. The velocities of the multiple bullets are more than four and less than fourteen times those in the case of a single bullet, for positive and negative voltage pulses, respectively. A detailed analysis shows that the charges carried by the bullets probably play an important role in the propagation of plasma bullets and in the formation of multiple bullets. It is found that the electrode polarity also plays an important role in the generation and propagation of multiple plasma bullets.

With increasing memory density of Flash EEPROM, the gate-induced drain leakage (GIDL) due to band-to-band tunneling during erase can become an important concern since millions of transistors are erased at the same time. In the common scheme of the double-diffused junction and source erase, an additional negative-gate bias can reduce the needed junction voltage for erase but does not reduce GIDL. Channel erase can eliminate GIDL entirely, however the required high negative voltage adds to circuit/process complexity. In this paper we show that the combination of LDD source and negative-gate erase can reduce GIDL by orders of magnitude using lower negative-gate voltage than that of the channel erase.

A single stack of double poled piezoelectric ceramic elements (202) create a monolaminar bender bar (200) which can be used in acoustic applications. The stack is lined up such that adjacent elements (202) in bender bar (200) have oppositely poled top and bottom sections. A positive voltage (230) is connected to electrical connection plates (214) which are positioned between every other piezoelectric element (202) in the stack and a negative voltage (232) is connected to electrical connection plates (214) which are between the remaining piezoelectric elements (202). Applying a voltage causes the stack to bend, wherein the piezoelectric elements (202) in the top half of the bender bar (200) all expand while the piezoelectric elements (202) in the bottom half of the bender bar (200) all contract.

The impulse withstand of insulating liquids in divergent fields is presently being studied with particular atten tion in regards foreseeable changes in the nature of mineral oils, and in regards the behavior of equipment subjected to lightning impulses. A draft standard is presently under study by the IEC. Tests based on this draft standard were undertaken on ten traditional naphthenic oils, and on three paraffinic oils developed in France. These tests indicated the following conclusions: the measurement cell must be adequately defined to obtain repeatable and reproducible results; it is unnecessary to treat new oils before testing; the value of the dielectric strength under negative impulse is always notably higher than the value under positive impulse (50% on average); the latter can therefore condition the behavior of equipment in operation; thermal ageing lowers the withstand under negative voltage (20% on average); under positive impulse, it may induce either a reduction or an increase of the withstand; paraffinic oils have a withstand voltage that is equal to or higher than that of naphthenic oils, depending on refining.

In view of the detrimental voltage transients associated with the automotive environment, and the advantages and limitations of the present bipolar integrated circuits with respect to this environment, new bipolar circuit and device innovations have been specifically developed to economically protect the IC from these destructive transients and improve the IC's functional performance. Many of these techniques prevent the negative voltage transients from injecting electrons into the P-type substrate, insuring that a newly defined parasitic lateral n-p-n transistor cannot degrade the performance of the IC. New and effective high-frequency input filtering techniques were also devised on the chip to prevent the high-frequency voltage transients from gaining access to the IC circuitry, especially at the logic inputs.

The effect of an applied, time varying voltage on the plastic behavior of (Hg,Cd)Te has been investigated. We observe that both positive and negative voltages suppress plasticity, with the negative voltage being more effective. The influence of this voltage polarity is strain dependent and provides information on the charge of the mobile dislocations. From these results we present a model of the strain dependence of the voltage dependent plasticity.