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52. Complementary polarity exposures for cost-effective line-cutting in multiple patterning lithography

Author

Chen, Frederick T., Chen, Wei-Su, Tsai, Ming-Jinn, and Ku, Tzu-Kun

Abstract

Multiple patterning is the only known way to extend current 193 nm immersion-based optical lithography beyond 40 nm half-pitch. A highly effective technique for multiple patterning uses self-aligned etched spacers to define the tightest pitch lines as critical features. However, to complete the patterning, the lines must be cut with at least one separate additional exposure. In order to reduce the costs associated with multiple cut locations, it is proposed to group the locations into portions of larger features. Specifically, the cut locations can be the intersection of the spacer lines and the overlap of at least two polygons of opposite exposure polarity. The cost reduction is determined by the reduced number of exposures, as well as the looser pitch and dimensions of the exposures. Besides cost reduction, greater immunity to exposure shot noise (if EUV or EBL is used for cutting) is provided by the use of larger polygons. The benefits of complementary polarity patterning based on these key issues will be analyzed for the 10 nm half-pitch application, and extensions to even smaller half-pitches will be discussed.

Published
2012
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53. Transfer optimized dry development process of sub-32nm HSQ/AR3 BLR resist pillar from low-K etcher to metal etcher

Author

Chen, Wei-Su, Chen, Peng-Sheng, Wei, Hung-Wen, Chen, Frederick T., Tsai, Ming-Jinn, and Ku, Tzu-Kun

Abstract

The optimized dry development condition of low-k etcher obtained before is transferred to and optimized in DPSII metal etcher in this study to avoid resist pillar collapse, etch residual magnification, process continuity and tool simplicity. Three key process parameters of oxygen flow rate, bottom power and e-chuck temperature are studied for vertical pillars with various pattern densities. HSQ pillar patterning is transferred from diluted Fox-12 to commercialized XR1541-002 where the film thickness and patterned CD are matched. LTN hard mask (HM) of 100 nm thick above RRAM film stack is deposited for reducing proximity effect of XR1541-002 and improving etch resistance. Experimental results are summarized below. Highest AR of ~3.9 for HSQ/AR3 BLR semi-dense L/S=1/3 pillar with vertical profile is obtained with optimized dry develop condition of O2, N2, flow rates, chamber pressure and temperature, top and bottom power of 8, 5, sccm, 3 mTorr, 80oC, 200 and 100 watts respectively. AR is lower for looser pattern density. Oxygen flow rate and bottom power are the most critical process parameters for obtaining high AR BLR pillar and most vertical profile of pillar, just like the case of low-k etcher. E-chuck temperature is critical in profile control. Etch residual is magnified to broaden LTN pillar CD and degrade CD uniformity (CDU) if its etch process is not immediately continued after dry development process.

Published
2012
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54. 28-nm 2T High-K Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes.

Author

Mei, Chin Yu, Shen, Wen Chao, Wu, Chun Hsiung, Chih, Yue-Der, King, Ya-Chin, Lin, Chrong Jung, Tsai, Ming-Jinn, Tsai, Kan-Hsueh, and Chen, Frederick T.

Subjects
TRANSISTORS, NONVOLATILE random-access memory, CMOS logic circuits, DIELECTRICS research, NONVOLATILE memory, INTEGRATED circuits
Abstract

A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high-k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/HfO2/SiO2/Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high-K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products. [ABSTRACT FROM AUTHOR]

Published
2013
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56. Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme.

Author

Chang, Meng-Fan, Kuo, Chia-Cheng, Sheu, Shyh-Shyuan, Lin, Chorng-Jung, King, Ya-Chin, Lin, Zhe-Hui, Su, Keng-Li, Chen, Yu-Sheng, Lin, Wen-Pin, Lee, Heng-Yuan, Tsai, Chen-Han, Chen, Wei-Su, Chen, Frederick T., Ku, Tzu-Kun, Kao, Ming-Jer, Tsai, Ming-Jinn, Wu, Jui-Jen, Chih, Yu-Der, and Natarajan, Sreedhar

Published
2013

59. Fast-Write Resistive RAM (RRAM) for Embedded Applications.

Author

Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Tai-Yuan Wu, Chen, Frederick T., Keng-Li Su, Ming-Jer Kao, and Ming-Jinn Tsai

Subjects
RANDOM access memory, EMBEDDED computer systems, MICROCONTROLLERS, COMPUTER storage devices, COMPUTER input-output equipment
Abstract

Editor's note:Especially for microcontroller and mobile applications, embedded nonvolatile memory is an important technology offering to reduce power and provide local persistent storage. This article describes a new resistive RAM device with fast write operation to improve the speed of embedded nonvolatile memories.—Leland Chang, IBM T.J. Watson Research Center [ABSTRACT FROM PUBLISHER]

Published
2011
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60. Size dependence of TiN/HfO2/Ti MIM ReRAM resistance states: Model and experimental results

Author

Chen, Frederick T., Lee, Heng-Yuan, Chen, Yu-Sheng, Chen, Pang-Shiu, Gu, Peggy, Chen, Chi-Wei, Hsu, Yen-Ya, Liu, Wen-Hsing, Chen, Wei-Su, Tsai, Ming-Jinn, Lo, Shen-Chuan, and Lai, Ming-Wei

Subjects
*TITANIUM nitride, *HAFNIUM oxide, *RANDOM access memory, *ELECTRIC resistance, *ELECTRIC insulators & insulation, *RADIAL basis functions
Abstract

Abstract: The size dependence of the resistance states of a TiN/HfO2/Ti resistance random access memory (ReRAM) metal–insulator–metal (MIM) structure is described in terms of the filament distribution within the structure. We introduce radial distribution functions to model process-induced effects on the density of percolating conduction paths in the oxide. A suitably chosen function can accurately model the size dependence of the HIGH resistance ReRAM state. On the other hand, the size independence of the LOW state is attributed to the selection of a dominant filament. Our experimental results match the proposed explanations very well, if the distribution of HIGH state conduction paths is dominated by process effects near the edge of the ReRAM cell, while the distribution of LOW state conduction paths is very localized somewhere within the ReRAM cell. [Copyright &y& Elsevier]

Published
2010
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