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In financial computation, Field Programmable Gate Arrays (FPGAs) have emerged as a transformative technology, particularly in the domain of option pricing. This study presents the impact of Field Programmable Gate Arrays (FPGAs) on computational methods in finance, with an emphasis on option pricing. Our review examined 99 selected studies from an initial pool of 131, revealing how FPGAs substantially enhance both the speed and energy efficiency of various financial models, particularly Black–Scholes and Monte Carlo simulations. Notably, the performance gains—ranging from 270- to 5400-times faster than conventional CPU implementations—are highly dependent on the specific option pricing model employed. These findings illustrate FPGAs' capability to efficiently process complex financial computations while consuming less energy. Despite these benefits, this paper highlights persistent challenges in FPGA design optimization and programming complexity. This study not only emphasises the potential of FPGAs to further innovate financial computing but also outlines the critical areas for future research to overcome existing barriers and fully leverage FPGA technology in future financial applications. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable image confusion scheme, which uses Linear Congruential Generators (LCGs)-based Pseudorandom Bits Generator (PRBG). The PRBG is based on the variable input-coupled LCG with a reconfigurable clock divider. The proposed algorithm encrypts the input image up to four times successively using different random sequences in every attempt. This new scheme aims to efficiently extract statistically strong pseudorandom sequences from a proposed PRBG with a large keyspace and simultaneously increase the security level of the encrypted image. This PRBG was initially designed on Virtex-5 (XC5VLX110T), Virtex-7 (XC7VX330T) and Artix-7 (XC7A100T) Field Programmable Gate Arrays (FPGAs). The statistical properties of the proposed PRBG for four different configurations are verified by the National Institute of Standards and Technology (NIST) tests. Thereafter, a reconfigurable encryption/decryption algorithm that uses the proposed PRBG is developed for secure image encryption. The encryption process was accomplished using the MATLAB tool after obtaining the PRBG keys from the FPGA. To show the quality and strength of the encryption process, security analysis [correlations and Number of Pixels Change Rate (NPCR)] is performed. Security analysis results are compared with the conventional encryption algorithm to show that the developed reconfigurable encryption scheme provides better results in security tests. [ABSTRACT FROM AUTHOR]

Summary Generating a quadrature signal in a single‐phase system using a second‐order generalized integrator (SOGI) requires accurate frequency information. The standard SOGI phase‐locked loop (PLL) includes frequency feedback to the SOGI. However, during grid abnormalities such as voltage sag/swell and phase angle jumps, the SOGI‐PLL faces frequency disturbances that propagate to the phase detector (PD) and affects the quadrature signal generator (QSG). Furthermore, the SOGI‐PLL having two loops dependent on each other creates loop coupling phenomena; either a change in phase or frequency affects each other. SOGI‐PLL is tuning sensitive, as the SOGI block has a gain that needs to be adjusted, increases the complexity, and affects the performance of the system. There is a trade‐off between SOGI gain and PLL parameters that needs to be considered for adequate parameter design to provide accurate grid synchronization while maintaining the stability of the system. To attain better performance, researchers have proposed derivative‐based PLL (DPLL). The conventional DPLL faces challenges to noise and harmonics amplification. This paper presents an improved DPLL for single‐phase grid synchronization under adverse grid conditions. The improved derivative‐based PLL (IDPLL) comprises two improved derivative‐based quadrature signal generator (IDQSG) blocks to extract the phase‐error information for accurately estimating phase and frequency. The detailed mathematical modeling and bode plot for the IDQSG and IDPLL are presented. The proposed IDQSG eliminates the requirement of gain tuning, hence reducing complexity. Moreover, there is no interdependent loop in the IDPLL, which significantly improves the dynamic performance. A hardware setup is developed to evaluate the performance of the system in real‐time. The experimental results are obtained using an field programmable gate array (FPGA)‐based controller. [ABSTRACT FROM AUTHOR]

The Karhunen-Loève transform (KLT) stands as a well-established discrete transform, demonstrating optimal characteristics in data decorrelation and dimensionality reduction. Its ability to condense energy compression into a select few main components has rendered it instrumental in various applications within image compression frameworks. However, computing the KLT depends on the covariance matrix of the input data, which makes it difficult to develop fast algorithms for its implementation. Approximations for the KLT, utilizing specific rounding functions, have been introduced to reduce its computational complexity. Therefore, our paper introduces a category of low-complexity, data-independent KLT approximations, employing a range of round-off functions. The design methodology of the approximate transform is defined for any block-length N , but emphasis is given to transforms of N = 8 due to its wide use in image and video compression. The proposed transforms perform well when compared to the exact KLT and approximations considering classical performance measures. For particular scenarios, our proposed transforms demonstrated superior performance when compared to KLT approximations documented in the literature. We also developed fast algorithms for the proposed transforms, further reducing the arithmetic cost associated with their implementation. Evaluation of field programmable gate array (FPGA) hardware implementation metrics was conducted. Practical applications in image encoding showed the relevance of the proposed transforms. In fact, we showed that one of the proposed transforms outperformed the exact KLT given certain compression ratios. [ABSTRACT FROM AUTHOR]

This article demonstrates the performance of back-to-back connected voltage source inverter (BTB-VSI)-based distribution static compensator (DSTATCOM). In the proposed system, a three-phase three wire electrical utility system (EUS) is integrated with distributed energy resources (DER) through BTB-VSI. It has drawn more attention due to enhanced active power filtering, simple design procedure and performs reliable operation. The objectives of the research work is to provide clean power for weak EUS with improved power quality (PQ) such as, better voltage regulation, improved power factor (P.F), reduced total harmonic distortion (THD), balanced voltage at point of common coupling (PCC) and better optimal active power flow control (OAPFC), and so on. An artificial neurocontrol technique Kernel Hebbian Least Mean Square (KHLMS) is chosen to determine the accurate reference source current for operation of voltage source inverter (VSI). The BTB-VSI performance is investigated on both shunt compensation and OAPFC. The proposed system is converted to a simulation model and hardware unit using MATLAB/Simulink software and SPARTAN−6 field programmable gate arrays (FPGA) controller. Finally, the Simulation and experimental results illustrate that the shunt compensating ability with OAPFC of BTB-VSI performs better over VSI as per IEEE Std 1159–2019 grid code. [ABSTRACT FROM AUTHOR]

Large resistive sensor arrays (RSAs) show great potential in tactile perception. However, the large number of sensors can result in great hardware overhead and bring difficulties for acquiring and processing mass data timely in transient measurement applications. This paper implements a field programmable gate array (FPGA)-based data processing system for a large RSA of 96 × 96, which shows good power consumption and high-speed wireless data update. For crosstalk-free measure, the zero potential method is improved with bus switches, leading to fewer operational amplifiers required and less negative power consumption. A real-time embedded data processing system is realized by FPGA for excellent parallel processing ability. A high-speed wireless transfer scheme with automatic regulated transfer size is proposed and realized by a wireless fidelity module, which allows timely data analysis at the remote end. Moreover, fault identification of RSAs fabricated by micro-electromechanical system technology is achieved. Tests carried out on a 32 × 32 RSA show that the total power consumption is 2209 mW, including 1261 mW of processors and 948 mW of readout circuits, corresponding to 2.15 mW/pixel. The total negative power consumption of 549 mW has been reduced by 50% compared with the zero potential method. The scanning speed is 400 fps, and the wireless transfer speed is up to 120 fps when the transceiver and receiver are 5 m apart. [ABSTRACT FROM AUTHOR]

This paper introduces a novel digital triangular–trapezoidal double-channel shaping algorithm to enhance the counting rate of resistive anode detectors. The algorithm is based on the trapezoidal shaping algorithm and improves it. At the extreme counting rate, the trapezoidal shaping algorithm cannot alleviate the pulse pileup, so the counting rate cannot meet the requirements of a high performance detector. The triangular–trapezoidal double-channel shaping algorithm is introduced in the resistance anode detector, which can replace the trapezoidal shaping filtering algorithm to process the output signal of the resistance anode detector and obtain the single photon position information. This improvement improves the counting rate of the resistor anode detector and reduces the resolution degradation caused by pulse pileup. The algorithm is simulated by System Generator software and implemented on FPGA (field programmable gate array). The triangular–trapezoidal double-channel shaping algorithm presented in this paper plays an important role in reducing electronic noise and pulse pileup. The algorithm is subjected to simulation testing, and it can recognize signals with a minimum pulse interval of 1 µs and counting rate up to 1000 kcps. [ABSTRACT FROM AUTHOR]

The radio spectrum is a scarce and extremely valuable resource that demands careful real-time monitoring and dynamic resource allocation. Dynamic spectrum access (DSA) is a new paradigm for managing the radio spectrum, which requires AI/ML-driven algorithms for optimum performance under rapidly changing channel conditions and possible cyber-attacks in the electromagnetic domain. Fast sensing across multiple directions using array processors, with subsequent AI/ML-based algorithms for the sensing and perception of waveforms that are measured from the environment is critical for providing decision support in DSA. As part of directional and wideband spectrum perception, the ability to finely channelize wideband inputs using efficient Fourier analysis is much needed. However, a fine-grain fast Fourier transform (FFT) across a large number of directions is computationally intensive and leads to a high chip area and power consumption. We address this issue by exploiting the recently proposed approximate discrete Fourier transform (ADFT), which has its own sparse factorization for real-time implementation at a low complexity and power consumption. The ADFT is used to create a wideband multibeam RF digital beamformer and temporal spectrum-based attention unit that monitors 32 discrete directions across 32 sub-bands in real-time using a multiplierless algorithm with low computational complexity. The output of this spectral attention unit is applied as a decision variable to an intelligent receiver that adapts its center frequency and frequency resolution via FFT channelizers that are custom-built for real-time monitoring at high resolution. This two-step process allows the fine-gain FFT to be applied only to directions and bands of interest as determined by the ADFT-based low-complexity 2D spacetime attention unit. The fine-grain FFT provides a spectral signature that can find future use cases in neural network engines for achieving modulation recognition, IoT device identification, and RFI identification. Beamforming and spectral channelization algorithms, a digital computer architecture, and early prototypes using a 32-element fully digital multichannel receiver and field programmable gate array (FPGA)-based high-speed software-defined radio (SDR) are presented. [ABSTRACT FROM AUTHOR]

Observation datasets acquired by the Hyper Suprime-Cam (HSC) on the Subaru Telescope for NASA's New Horizons mission target search were analyzed through a method devised by JAXA. The method makes use of Field Programmable Gate arrays and was originally used to detect fast-moving objects such as space debris or near-Earth asteroids. Here we present an application of the method to detect slow-moving Kuiper Belt Objects (KBOs) in the New Horizons target search observations. A cadence that takes continuous images of one HSC field of view for half a night fits the method well. The observations for the New Horizons Kuiper Belt Extended Mission (NH/KEM) using HSC began in 2020 May, and are ongoing. Here we show our result of the analysis of the dataset acquired from 2020 May through 2021 June that have already passed the proprietary period and are open to the public. We detected 84 KBO candidates in the 2020 June and 2021 June datasets, when the observation field was close to opposition. [ABSTRACT FROM AUTHOR]

Precise radar pulse detection is the premise of electronic support measures. A constant false alarm rate (CFAR) detection algorithm based on difference of box (DOB) filter is proposed to realise low‐complexity and environment‐adaptive radar pulse detection, and the principle behind the proposed algorithm is revealed. Specifically, the DOB filter is adopted to extract the rising edges and falling edges of radar pulses, and the signal variation law of probability density functions (PDFs) during the process of DOB filter are first theoretically analysed. Based on the derived PDFs, dynamic detection threshold and fixed threshold factor for the proposed CFAR algorithm based on DOB filter are deduced to detect the presence of radar pulses. Furthermore, the closed‐form expression of the detection probability is derived. Simulations and on‐board field programmable gate arrays implementation verify the superiority of the proposed CFAR algorithm based on DOB filter. Simulation results show that the proposed algorithm performs well in detecting various types of pulse signals, the detection probability ≥99% on condition that the signal‐to‐noise ratio ≥3 dB and false alarm probability = 10−8. Moreover, the proposed CFAR algorithm based on DOB filter can deal with both singular pulses and pulse on pulse signals. [ABSTRACT FROM AUTHOR]

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community's quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image. [ABSTRACT FROM AUTHOR]

We experimentally demonstrate a scheme for generating massively parallel and real-time physical random bits (PRBs) by using weak-resonant-cavity Fabry-Perot laser diodes (WRC-FPLDs) with optical feedback. By using external optical feedback to modify the nonlinear dynamic behavior of the longitudinal modes in WRC-FPLDs, the chaotic behavior of each channel can be induced under suitable feedback strength. By filtering these longitudinal modes, a real-time PRBs at 10 Gbits/s can be generated by using field programmable gate array (FPGA) board for the real-time post-processing of a single-channel chaotic signal. Considering the presence of up to 70 longitudinal modes within a broad spectral range exceeding 40 nm, each of these modes can be used to extract chaotic time sequences for random number generation. Therefore, our PRB generation scheme has the potential to achieve a data throughput of over 700 Gbits/s. [ABSTRACT FROM AUTHOR]

Multi-motor servo systems are widely used in industrial control. However, the single-core microprocessor architecture based on the microcontroller unit (MCU) and digital signal processor (DSP) is not well suited for high-performance multi-motor servo systems due to the inherent limitations in computing performance and serial execution of code. The bus-based distributed architecture formed by interconnecting multiple unit controllers increases system communication complexity, reduces system integration, and incurs additional hardware and software costs. Field programmable gate array (FPGA) possesses the characteristics of high real-time performance, parallel processing, and modularity. A single FPGA can integrate multiple motor servo controllers. This research uses MCU + FPGA as the core to realize high-precision multi-axis real-time control, combining the powerful performance of the MCU processor and the high-speed parallelism of FPGA. The MCU serves as the central processor and facilitates data interaction with the host computer through the controller area network (CAN). After data parsing and efficient computation, MCU communicates with the FPGA through flexible static memory controller (FSMC). A motor servo controller intellectual property (IP) core is designed and packaged for easy reuse within the FPGA. A 38-axis micro direct current (DC) motor control system is constructed to test the performance of the IP core and the heterogeneous embedded platforms. The experimental results show that the designed IP core exhibits robust functionality and scalability. The system exhibits high real-time performance and reliability. [ABSTRACT FROM AUTHOR]

Orthogonal Time Frequency Space (OTFS) modulation is proposed to support high-speed and reliable vehicular communication scenarios, which is a novel two-dimensional (2D) delay-Doppler domain modulation technique. Compared with traditional modulation schemes such as orthogonal frequency division multiplexing (OFDM), OTFS has displayed better performance in very high-mobility wireless channels. In this work, we have proposed the novel VLSI architecture for OTFS in the Additive White Gaussian Noise (AWGN) channel condition and shown the resource utilization report of our proposed architecture to implement on Field Programmable Gate Array (FPGA) board, along with the relationship between inputs and outputs of the OTFS signal in the delay-Doppler domain. [ABSTRACT FROM AUTHOR]

Massive computational complexity and memory requirement of artificial intelligence models impede their deployability on edge computing devices of the Internet of Things (IoT). While Power-of-Two (PoT) quantization is proposed to improve the efficiency for edge inference of Deep Neural Networks (DNNs), existing PoT schemes require a huge amount of bit-wise manipulation and have large memory overhead, and their efficiency is bounded by the bottleneck of computation latency and memory footprint. To tackle this challenge, we present an efficient inference approach on the basis of PoT quantization and model compression. An integer-only scalar PoT quantization (IOS-PoT) is designed jointly with a distribution loss regularizer, wherein the regularizer minimizes quantization errors and training disturbances. Additionally, two-stage model compression is developed to effectively reduce memory requirement, and alleviate bandwidth usage in communications of networked heterogenous learning systems. The product look-up table (P-LUT) inference scheme is leveraged to replace bit-shifting with only indexing and addition operations for achieving low-latency computation and implementing efficient edge accelerators. Finally, comprehensive experiments on Residual Networks (ResNets) and efficient architectures with Canadian Institute for Advanced Research (CIFAR), ImageNet, and Real-world Affective Faces Database (RAF-DB) datasets, indicate that our approach achieves 2×∼10× improvement in the reduction of both weight size and computation cost in comparison to state-of-the-art methods. A P-LUT accelerator prototype is implemented on the Xilinx KV260 Field Programmable Gate Array (FPGA) platform for accelerating convolution operations, with performance results showing that P-LUT reduces memory footprint by 1.45×, achieves more than 3× power efficiency and 2× resource efficiency, compared to the conventional bit-shifting scheme. [ABSTRACT FROM AUTHOR]

Epilepsy is a serious neurological disorder that results in seizures. It can be diagnosed by analyzing the brain's electrical activity using an electroencephalogram (EEG). However, the detection of seizures from massive EEG datasets is a challenging task. To address this challenge, researchers have developed several machine‐learning classifiers and feature extraction techniques for detecting seizures. This paper proposes an energy‐efficient and fast field programmable gate array (FPGA) architecture for detecting epileptic seizures using minimal computational resources. The seizure detection system uses the one Hjorth parameter (mobility) and another statistical parameter (nonlinear energy) as features and employs two efficient classifiers, quadratic discriminant analysis and linear support vector machine (LSVM), for classifying signals into seizure and nonseizure categories. The feature extractor block is connected individually to each of these classifiers. Subsequently, the performance of these two proposed models is evaluated in terms of accuracy, sensitivity, power consumption, resource utilization, and other metrics. The results demonstrate that the SVM classifier‐based model achieved the highest accuracy (99.4%) and sensitivity (98.8%) while consuming minimal dynamic power (0.057 mW) and utilizing the minimum FPGA resources. Thus, the proposed hardware system offers a reliable and energy‐efficient solution for detecting seizures in clinical and real‐time applications. [ABSTRACT FROM AUTHOR]

Aiming at the flicker problem faced by vehicle streaming media rearview mirror under LED signal light environment, meanwhile, considering the impact of rapid local image motion and complex edge textures on image restoration, a real-time flicker mitigation system based on FPGA(Field Programmable Gate Array) is proposed in this paper. Firstly, the constraint conditions of the flicker pixels are established according to the features of flicker images such that the flicker region are efficiently detected through three consecutive frames. Then, a motion estimation algorithm based on neighborhood images groups is proposed, the image matching criterion is improved, and the neighborhood images vectors is clustered to enhance image inpainting effect in complex scene. Finally, a parallel pipeline processing architecture for video data streams is designed based on the ZYNQ(ZYNQ-7000 All Programmable SoC) platform to achieve system acceleration. The experimental results show that the proposed system can satisfy the real-time processing requirement of 800x480 resolution and 30 fps video, and has good mitigation effect on flickering images in complex scenes. [ABSTRACT FROM AUTHOR]

Background: Sequence alignment lies at the heart of genome sequence annotation. While the BLAST suite of alignment tools has long held an important role in alignment-based sequence database search, greater sensitivity is achieved through the use of profile hidden Markov models (pHMMs). Here, we describe an FPGA hardware accelerator, called HAVAC, that targets a key bottleneck step (SSV) in the analysis pipeline of the popular pHMM alignment tool, HMMER. Results: The HAVAC kernel calculates the SSV matrix at 1739 GCUPS on a ∼ $3000 Xilinx Alveo U50 FPGA accelerator card, ∼ 227× faster than the optimized SSV implementation in nhmmer. Accounting for PCI-e data transfer data processing, HAVAC is 65× faster than nhmmer's SSV with one thread and 35× faster than nhmmer with four threads, and uses ∼ 31% the energy of a traditional high end Intel CPU. Conclusions: HAVAC demonstrates the potential offered by FPGA hardware accelerators to produce dramatic speed gains in sequence annotation and related bioinformatics applications. Because these computations are performed on a co-processor, the host CPU remains free to simultaneously compute other aspects of the analysis pipeline. [ABSTRACT FROM AUTHOR]

Recent advancements in communication technologies have highlighted the pivotal role of information security for all individuals and entities. In response, researchers are increasingly focusing on cryptographic solutions to ensure the reliability of confidential information. Recognizing the superiority of chaotic systems preference as entropy source of cryptographic systems, this paper proposes a novel true random number generator (TRNG) design by combining four different chaotic systems outputs, tailored for real-time video encryption application. These chaotic systems are continuous-time Lorenz and fractional-order Chen-Lee systems, as well as discrete-time Logistic and Tent maps. This study generates true random bit (TRB) sequences at a high bit rate (25 Mbps) through the hardware implementations of four distinct chaotic systems to have the best statistical randomness in the resulting output. Then, the cryptographic true random key bits (8-bit at 25 MHz frequency) are employed in the post-processing with real-time video data by using the XOR operation, a fundamental post-processing algorithm. The real-time video encryption application is executed on an experimental assembly, composed of a Field Programmable Gate Array (FPGA) development kit, an OV7670 camera module, a VGA monitor, and prototype circuit boards for the chaotic systems. To evaluate the effectiveness of the proposed encryption system, several security assessments are conducted. These include NIST SP 800 − 22 statistical tests, FIPS 140-1 standards, chi-square tests, histogram and correlation analysis, and NPCR and UACI differential attack resilience tests. Consequently, the findings suggest that the presented real-time embedded cryptosystem is robust and suitable for secure communications, particularly in the realm of video transmission. [ABSTRACT FROM AUTHOR]

This article describes the core implementation of an Advanced Encryption Standard - AES in Field Programmable Gate Array - FPGA. The core was implemented in both Xilinx Spartan-3 and Xilinx Virtex-5 FPGAs. The algorithm was implemented for 128 bits word and key. The implementation was very efficient, achieving 318MHz on a Xilinx Spartan-3, representing at 50% faster than other reported works. The implementation can achieve 800MHz on a Xilinx Virtex-5. The main goal of this work was the implementation of a fast and modular AES algorithm, as it can be easily reconfigured to 128, 196 or 256 bits key, and can find a wide range of applications. Nevertheless, all the reported works used as comparison basis to our work were also implemented using 128 bits key. [ABSTRACT FROM AUTHOR]

Field Programmable Gate Arrays (FPGAs) have witnessed an increase in space applications in the last years, mainly due to their cost-effective high-performances and flexibility. However, the susceptibility of these devices to radiation-induced effects when working in such an environment is well known. When common mitigation techniques are not sufficient to ensure the correct completion of a task, radiation-hardened FPGAs represent one of the most effective solutions. NanoXplore, in this context, is the first European developer of rad-hard FPGAs, which embed intrinsic high complexity in their architectures preventing the user from using or developing custom placement and routing algorithms. In this paper, we overcame these issues by proposing the first tool tailored to NanoXplore devices which allows the exploration of NanoXplore device architectures and routing of points through a Python interface. We developed a model that reflects the one used by the vendor, allowing the user to extract info about routes, nets and additional logic, otherwise unavailable. The tool also performs routing of points in the programmable logic, computing the optimal path. An implementation of the router on Graphic Processing Unit (GPU) is proposed to exploit the highly parallelizable nature of the problem. Finally, routing timing analyses on different benchmarks have been performed, improving the routing routine time. [ABSTRACT FROM AUTHOR]

Biological systems undergo constant dynamic changes across various spatial and temporal scales. To investigate the intricate biological dynamics in living organisms, there is a strong need for high-speed and high-resolution imaging capabilities with significant imaging depth. In this work, we present high-spatiotemporal resolution microwave-induced thermoacoustic tomography (HR-MTAT) as a method for imaging biological dynamics in deep tissues. HR-MTAT utilizes nanosecond pulsed microwave excitation and ultrasound detection, with appropriate spatial configurations, to achieve high coupling of the sample to the microwaves, to produce images in soft tissue with dielectric contrast and sub-millimeter spatial resolution (230 μm), to a depth of a few centimeters. Notably, by employing a 128-channel parallel signal acquisition and digitization strategy, the field programmable gate array module manages data synthesis, and GPU-based parallel pixel reconstruction facilitates HR-MTAT to accomplish single-frame image reconstruction in an impressive 50 μs. The practical feasibility of HR-MTAT was evaluated in live mice. The results show that HR-MTAT can noninvasively image whole-body small animals (up to 60 mm in depth) with clear resolution of internal organ structures at a frame rate of 100 Hz, without the need for labeling. At this high spatiotemporal resolution, HR-MTAT can capture respiration, heartbeat, and arterial pulse propagation without motion artifacts and track bio-nanoprobes in livers and tumors. These findings demonstrate HR-MTAT's ability to perform dynamic imaging with high contrast and resolution in deep tissues. [ABSTRACT FROM AUTHOR]

The rise of three-dimensional (3D) IC layouts necessitates the development of unique partitioning methods that will be suitable for the 3D component designs. Net lists partitioning is a key aspect of the physical design of a 3D IC. Reducing wire lengths between gates is possible with 3D-ICs since they have a small footprint as well as vertical connectivity among dies. As a result, they consume less power and have shorter connection delays. This paper presents an efficient genetic algorithm (GA) based layer partitioning technique for 3D ICs that focuses on proper layer assignment to reduce area deviation and minimization of Through Silicon Vias (TSVs) to reduce IC footprint. The method starts with random initial solutions and refines the solutions with efficient crossover and mutation operator till the optimized solution is achieved. Our methodology produces high-quality solutions on well-known benchmarks. The experimental findings are compared with state-of-the-art methodologies and the suggested strategy is found to be very effective in the case of decreasing the TSV count and space need of the 3-dimensional IC design. In addition, the performance of our strategy is also compared with two recent publications that use GA and Particle Swarm Optimization (PSO) and it is found that the proposed method achieves 20.18% and 38.66% average reduction in terms of TSV count respectively. Thus, the suggested technique is beneficial for multilayered 3D IC partitioning, as it can reduce TSV count while also satisfying balancing criteria and latency. [ABSTRACT FROM AUTHOR]

Synthetic aperture radar (SAR) is a powerful tool in remote sensing applications that can produce high-resolution images and operate in any weather condition. It is composed of many RF components, such as the IQ mixer, which mixes the base chirp signal (IF) with the carrier signal (LO) and increases the bandwidth of the transmitted signal to twice the maximum frequency of the base chirp signal, reducing the workload of Programmable Field Gate Arrays (FPGA) and increasing the resolution of the SAR system. This research proposes a power combiner–splitter design that will be used as a supporting component to construct the IQ mixer in SAR applications based on a rat-race coupler. The measurement results show that the coupler has good S-parameter values.  S 11 ,  S 22 , and  S 33  have a low reflection value below −17 dB,  S 13  has a high isolation value below −22 dB, and  S 21  and  S 31  have a low attenuation value below −4 dB with amplitude unbalance below 0.1 dB and phase unbalance below 1 ° . The 150 MHz requirement bandwidth for the RF signal is also achieved. [ABSTRACT FROM AUTHOR]

The utilisation of continuous random waveforms for radar, that is, noise radar, has been extensively studied as a candidate for low probability of intercept operation. However, compared with the more traditional pulse‐Doppler radar, noise radar systems are significantly more complicated to implement, which is likely why few systems exist. If noise radar systems are to see the light of day, system design, implementation, limitations etc., must be investigated. Therefore, the authors examine and detail the implementation of a real‐time noise radar system on a field programmable gate array. The system is capable of operating with 100% duty cycle, 200 MHz bandwidth, and 268 ms integration time while processing a range of about 8.5 km. Additionally, the system can perform real‐time moving target compensation to reduce cell migration. System performance is primarily limited by the memory bandwidth of the off‐chip dynamic random access memory. [ABSTRACT FROM AUTHOR]

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The subject of study in this article is the models, methods, and principles of organization of entire lifecycle of Artificial Intelligence (AI) as a Service implemented with the use of Field Programmable Gate Array (FPGA). The purpose of this work is the improvement of the methodology of the deployment of dependable FPGA-based Artificial Intelligence as a Service by creating a complex of mutually agreed concept, principles, models, and methods considering the specifics of the use of heterogeneous computations of Artificial Intelligence and the possibility of realizing the unified protection of FPGA implementations. Tasks: to clarify the taxonomy of the dependability term within the proposed methodology; to propose the concept of deployment of dependable FPGA-based heterogeneous computations of Artificial Intelligence as a Service; to formulate the principle of tracing changes in FPGA projects and integrated environments during the entire lifecycle; to formulate the principle of unification of protection of FPGA implementations of heterogeneous computing of Artificial Intelligence as a Service; to formulate the principle of the product-service assessment of the availability of FPGA as a Service; and to discuss the promising directions of heterogeneous computations of AI. According to the tasks, the following results were obtained. The existing concepts of dependable systems deployment are discussed. The concept of the deployment of computations of Artificial Intelligence as a Service, which is obtained based on the improvement of paradigms of the creation and deployment of dependable systems and services, is proposed. The principle of tracing of changes, which assumes the updating of requirements during the lifecycle of FPGA projects, is proposed. The principle of the unification of protection, which combines and joins the consideration of various unique features of the FPGA instance to protect the implementation and the set of cyberthreats for the service as a whole, is proposed. The principle of the product-service assessment, which considers parameters and indicators of availability, is proposed. The perspective of the progress of nonelectronic mediums for heterogeneous computations with the use of a photonic implementations of Artificial Intelligence computations to ensure improved performance and reduced energy consumption is discussed. Conclusions. One of the main contributions of this research is that in the proposed methodology, the set of principles, models, and methods of deployment of Artificial Intelligence as a Service under conditions of changing requirements and integrated environments, and the need for mechanism of licensing protection of each instance of the system are developed, which allows to reduce model uncertainty by considering various stages of the lifecycle of dependable FPGA implementation using heterogeneous computations. [ABSTRACT FROM AUTHOR]

This paper presents the creation and realization of a precision time base (PTB) for mitigating jitter and measuring time interval error (TIE) in digital sampling oscilloscopes (DSO), achieved through the utilization of a field programmable gate array (FPGA). Our proposed method focuses on mitigating jitter through PTB, which involves the sampling of two reference channels having a phase shift of approximately 90∘ (at quadrature) for an accurate timebase correction. Through extensive experimentation and analysis, we were able to achieve a reduction in root mean square (RMS) jitter, minimizing it to around 260 fs. This outcome demonstrates the effectiveness of our approach in enhancing the accuracy and reliability of DSO measurements. Expanding on the application of our previously proposed technique, we demonstrate that the same sampling error correction approach can be utilized for TIE measurement. By sampling a large amount of data at either the rising or falling edge of a sinusoidal signal, TIE can be accurately evaluated. This extension enhances the versatility of our FPGA-based implementation by enabling comprehensive TIE analysis alongside PTB compensation in DSOs. [ABSTRACT FROM AUTHOR]

The importance of crucial current technical advancements, particularly those centered on the cryptography process such as Cryptographic advanced encryption standard (AES) hardware architectures are gaining momentum with respect to improving the speed and area optimizations. In this paper, we have proposed a novel architecture to implement AES on a reconfigurable hardware i.e., field programmable gate arrays (FPGA). The controller in AES algorithm is responsible to generate the signals to perform operations to generate the 128 bits ciphertext. The proposed controller uses multiplexer and synchronous register-based approach to obtain area and speed efficient on the FPGA hardware. The entire architecture of AES with proposed controller is implemented on Virtex 5, Virtex 6, and Virtex 7series using XilinxISE 14.7 and tested for critical path delay, frequency, slices, efficiency and throughput. It is observed that all the parameters are improved compared to existing architectures achieving the throughput of 32.29, 40.01, and 43.01 Gbps respectively. The key benefit of this approach is the high level of parallelism it displays in a quick and efficient manner. [ABSTRACT FROM AUTHOR]

The controller area network (CAN) remains the de facto standard for intra-vehicular communication. CAN enables reliable communication between various microcontrollers and vehicle devices without a central computer, which is essential for sustainable transportation systems. However, it poses some serious security threats due to the nature of communication. According to caranddriver.com, there were at least 150 automotive cybersecurity incidents in 2019, a 94% year-over-year increase since 2016, according to a report from Upstream Security. To safeguard vehicles from such attacks, securing CAN communication, which is the most relied-on in-vehicle network (IVN), should be configured with modifications. In this paper, we developed a configurable CAN communication protocol to secure CAN with a hardware prototype for rapidly prototyping attacks, intrusion detection systems, and response systems. We used a field programmable gate array (FPGA) to prototype CAN to improve reconfigurability. This project focuses on attack detection and response in the case of bus-off attacks. This paper introduces two main modules: the multiple generic errors module with the introduction of the error state machine (MGEESM) module and the bus-off attack detection (BOAD) module for a frame size of 111 bits (BOAD111), based on the CAN protocol presenting the introduction of form error, CRC error, and bit error. Our results show that, in the scenario with the transmit error counter (TEC) value 127 for switching between the error-passive state and bus-off state, the detection times for form error, CRC error, and bit error introduced in the MGEESM module are 3.610 ms, 3.550 ms, and 3.280 ms, respectively, with the introduction of error in consecutive frames. The detection time for BOAD111 module in the same scenario is 3.247 ms. [ABSTRACT FROM AUTHOR]

Induction surface hardening (ISH) processes are widely used in the heat treatment of numerous industrial components, especially in the automotive industry. Since this industry operates under very demanding quality standards, it is crucial for these heat treatment processes to meet rigorous specifications to ensure the safety and reliability of the produced components. This implies the precise and repeatable control of certain parameters throughout the manufacturing process of each of the parts treated, through precise and reliable instrumentation in electromagnetically harsh environments. The main objective of this work is to define the monitoring process for an industrial IHS application, determining the control needs and the methods of measurement, recording, and verification of the parameters that ensure the quality of the process. This paper describes the monitoring process of induction surface hardening, emphasizing the use of sensors and modern measurement and control systems. A comprehensive monitoring system supported by a programmable logic controller (PLC) and mixed acquisition and instrumentation systems (analog and digital) implemented with a high-performance Field Programmable Gate Array (FPGA) will be presented. [ABSTRACT FROM AUTHOR]

This paper presents the algorithmic framework for a multimodal hearing aid (HA) prototype designed on a Field Programmable Gate Array (FPGA), specifically the RFSOC4*2 AMD FPGA, and evaluates the transmitter performance through simulation studies. The proposed architecture integrates audio and video inputs, processes them using advanced algorithms, and employs the 5G New Radio (NR) communication protocol for uploading the processed signal to the cloud. The core transmission utilizes Orthogonal Frequency Division Multiplexing (OFDM), an algorithm that effectively multiplexes the processed signals onto various orthogonal frequencies, enhancing bandwidth efficiency and reducing interference. The design is divided into different modules such as Sound reference signal (SRS), demodulation reference signal (DMRS), physical broadcast channel (PBCH), and physical uplink shared channel (PUSCH). The modulation algorithm has been optimized for FPGA parallel processing capabilities, making it better suited for the hearing aid requirements for low latency. The optimized algorithm achieves a transmission time of only 4.789 ms and uses fewer hardware resources, enhancing performance in a cost-effective and energy-efficient manner. [ABSTRACT FROM AUTHOR]

Recent studies have focused on user authentication methods that use biometric signals such as electrocardiogram (ECG) and photo-plethysmography (PPG). These authentication technologies have advantages such as ease of acquisition, strong security, and the capability for non-aware authentication. This study addresses user authentication using electromyogram (EMG) signals, which are particularly easy to acquire, can be fabricated in a wearable form such as a wristwatch, and are readily expandable with technologies such as human–machine interface. However, despite their potential, they often exhibit lower accuracy (approximately 90%) than traditional methods such as fingerprint recognition. Accuracy can be improved using complex algorithms and multiple biometric authentication technologies; however, complex algorithms use substantial hardware resources, making their application to wearable devices difficult. In this study, a simple Siamese model with long short-term memory (LSTM) (SSiamese-LSTM) is proposed to achieve a high accuracy of over 99% with limited resources suitable for wearable devices. The hardware implementation was accomplished using field-programmable gate arrays (FPGAs). In terms of accuracy, EMG measurement results from Chosun University were used, and data from 100 individuals were employed for verification. The proposed digital logic will be integrated with an EMG sensor in the form of a watch that can be used for user authentication. [ABSTRACT FROM AUTHOR]

The increasing reliance on telecommunication technologies across various domains has raised concerns surrounding data security and privacy during transmission. In response to these concerns, this study introduces a different approach to cryptographic algorithm construction, utilizing cellular automata (CA). The idea involves designing an encryption algorithm based on a specific class of one-dimensional CA, incorporating elementary evolution rules specifically constructed to establish a reversible system, thereby enhancing information preservation and security. The encryption process involves forward iteration of the system, while decryption employs backward iteration, both processes being based on the same rule. Classified as a symmetric key cryptosystem within the stream cipher framework, the proposed algorithm was implemented using a Field Programmable Gate Array (FPGA) device (XILINX Spartan3E) at the hardware-level, complemented by software applications developed using the C# programming language. Testing on the experimental findings was conducted to check the efficacy of the proposed algorithm in ensuring information security and randomness, confirming its viability for practical encryption applications. [ABSTRACT FROM AUTHOR]

This paper introduces a low-complexity start–stop true random number generator (TRNG) utilizing jitter in ring oscillators (ROs). Incorporating phase detectors enhances entropy extraction from the same number of ROs. The raw bits undergo online post-processing using the SHA-1 algorithm, which is widely supported by many programming languages. The output bit streams pass all NIST statistical tests (SP 800-22 and SP-90B). Bits are generated on demand, enhancing security by preventing eavesdropping during continuous bit production. The TRNG maintains its performance regardless of the FPGA manufacturer. [ABSTRACT FROM AUTHOR]

Engineering can enhance students' theoretical knowledge and practical application skills when integrated into K‐12 education. This approach encourages students to contemplate technology and engineering in more depth. Field programmable gate array (FPGA) technology training is becoming increasingly important, especially for vocational high school technical teachers. This study focuses on providing FPGA technology training to these vocational and technical teachers. The aim is to improve their theoretical understanding of FPGA digital design and practical application skills. By incorporating the latest technology into their courses, educators can offer students in‐depth learning and practical experience in electronic engineering and digital design. The training program covered the basics of FPGA, its applications, and how it can benefit vocational high schools in laboratory environments. A total of 34 technical teachers participated in the training program. The effectiveness of the program was evaluated through pre‐ and posttraining questionnaires. The results showed that most of the questionnaire items were statistically and practically significant and varied according to the teachers' department, teaching experience, and level of education. [ABSTRACT FROM AUTHOR]

This article presents hardware architectures for computing four types of the 8‐point cosine transforms over the finite field F28$\mathbb {F}_{2^8}$. The proposed architectures utilize three distinct approaches, described in SystemVerilog, and are synthesized on a field‐programmable gate array (FPGA) SoC platform. To implement the design, an improved version of a standard F28$\mathbb {F}_{2^8}$ multiplier is presented by precomputing the required constants, thereby reducing hardware complexity. The system is integrated as a memory‐mapped Dual Core Cortex A9 peripheral to test the proposed architecture in the employed FPGA SoC. Among the three proposed architectures, one can choose to work up to 218.39 MHz, using 626 Logic Elements (LE) and 608 one‐bit registers; work up to 171 MHz, using 313 LE and 128 one‐bit registers; or work up to 197.36 MHz, at the cost of 350 LE and 293 one‐bit registers. [ABSTRACT FROM AUTHOR]