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This paper presents a comparison on Complementary and Recycling FC Amplifier. Complementary folded cascode amplifier is having large O/P swing with high gain of ordinary amplifier in complementary form. This is important to re-circuit again and again for their better slew rate, gain, bandwidth and transconductance. Recycling FC amplifier is similar to complementary FC amplifier and power can be recycled with few input parameters, to make simpler and easy to analyse. The cascode amplifier is connected with common source terminal and common gate terminal. The bandwidth of cascode amplifier is high because of the miller effect, it is eliminated. The system is connected with cascode and overall gain is high, takes few transistors for design of a cascode amplifier. A SR can allow frequency up to the range for that will eliminates unwanted signal. A unity gain bandwidth is applied to eliminate smaller signal. A SR of complementary FC amplifier is good at 3.3V/µs where as 6.3V/µs is for recycling folded cascode amplifier. The power consumption is 690µW and 710µW of complementary folded cascode and recycling folded cascode amplifier respectively. The voltage gain is above 70.7% of is considered as amplification for all ranges of its amplitude.

In this script, authors affirm a novel structure of tunnel FET in which a lightly doped channel region completely bounds the ultra-thin finger-like source region to enhance the tunneling probability with an increased tunneling interface area. TFETs have become common in power-constrained applications due to the minimal subthreshold swing (SS) and low OFF current ( $$I_\mathrm{{off}}$$ ) with low ON-state driving current ( $$I_\mathrm{{on}}$$ ) and ambipolar conduction concerns. Decreasing device dimensions is becoming more crucial for protecting device linearity and reliability under varying manufacturing and environmental conditions. However, changes in ambient temperature (T) imply its efficiencies, such as linearity distortion, analogue, and high-frequency performance, which must be thoroughly investigated. The impactful analysis was carried out for manuscript for assuring analog/RF performance, linearity distortion, and reliability of F-shaped TFET. Extensive investigations have been performed to check device susceptibility towards temperature ranging from 250 to 400 K by using the 2D-TCAD tool. For this, various critical parameters like $$I_\mathrm{{on}}$$ , $$I_\mathrm{{ambi}}$$ , SS, parasitic capacitances, threshold voltage ( $$V_\mathrm{{th}}$$ ), $$I_\mathrm{{on}}/I_\mathrm{{off}}$$ ratio, transconductance ( $$g_{m}$$ ), output transconductance ( $$g_\mathrm{{ds}}$$ ), higher-order $$g_{m}$$ ( $$g_{m2}$$ and $$g_{m3}$$ ), intrinsic gain (IG), cut-off frequency ( $$f_{t}$$ ), gain bandwidth product (GBP), transconductance generation factor (TGF), transit time (TT), transconductance frequency product (TFP), VIP2, VIP3, IIP3, IMD3 and 1-dB compression point have been investigated for temperature sensitivity analysis for the proposed device. Furthermore, reliability analysis is also performed, which shows that with a significant change in second harmonics, rising temperature is seen to be unfavorable for the SS, $$I_\mathrm{{ambi}}$$ and $$I_\mathrm{{on}}/I_\mathrm{{off}}$$ ratio.

A time-based operational amplifier (OP-AMP) with high gain and a wide bandwidth is presented in this paper. The proposed OP-AMP utilizes voltage-controlled oscillator (VCO) as an ideal integrator to replace the conventional voltage-based error amplifier which provides infinite DC gain. The OP-AMP is compensated with a feed-forward G m amplifier with capability of driving load capacitance up to 200pF. Proposed OP-AMP uses only 2pF of on-chip capacitor and consumes low quiescent current (70μA at typical corner and temperature). It further utilizes time-based offset cancellation technique to reduce the effect of mismatch between VCOs. The proposed OP-AMP was designed in TSMC 65nm CMOS LP process technology with input/output common mode voltages as 0.3V-0.7V and input power supply of 1.2V; achieving unity gain bandwidth (UGB) of 36MHz. A case study involving reference buffer for a 12-bit SAR ADC and a track and hold circuit are presented to demonstrate the versatility and performance of the proposed OP-AMP.

A modified recycling folded cascode (MRFC) operational transconductance amplifier (OTA) for achieving high DC gain, slew rate, and unity gain bandwidth (UGB) is proposed in this paper. Positive feedback is adopted to enhance DC gain and unity gain bandwidth. The proposed MRFC OTA is compared with conventional folded cascode (FC), recycling folded cascode (RFC), and other OTAs existing in the literature. Three OTAs, FC, RFC, and MRFC, are realized and implemented using the UMC 180 nm CMOS process for the same bias current of 300 $\mu$A. The designs are simulated in the Cadence Spectre Environment. From the simulation results, it may be noted that the proposed amplifier achieves a gain of 76.24 dB and unity gain bandwidth of 74.7 MHz with an input referred noise and slew rate of 139.2 $\mu V_{rms}$ and 64.05 V/$\mu$s respectively. The proposed amplifier occupies an area of 2760 $\mu m^{2}$.

This paper presents a technique to enhance an overall performance of advanced recycling folded cascode operational transconductance amplifier (RFC OTA). It adopts an input stage comprising a cross coupled MOS differential pair biased by a constant DC current source in addition to an adjustable floating voltage source. The proposed modification shows a substantial improvement in transconductance leading to boost dc gain, gain-bandwidth and slew rate of conventional FC-OTA. The structure is designed and implemented in 0.18 μm CMOS technology. In addition to transconductance enhancement, a remarkable improvement in a phase margin is achieved using a Miller compensation technique to ensure the stability of OTA. The simulation results demonstrate the performance of the proposed OTA with 72 dB gain and unity gain bandwidth of 128 MHz for a capacitive load of 10 pF. The modified RFC OTA shows 550% improvement in gain bandwidth product (GBW) and 20 dB hike in the gain compared to the conventional FC-OTA, which has 19.85 MHz GBW and 51.9 dB respectively. The Miller compensated OTA shows 36% improvement in a phase margin compared to non-compensated OTA with a slight reduction of 6% in GBW.

This work investigates design consideration of Gate Electrode Workfunction Engineered (GEWE) silicon nanowire MOSFET at room temperature. It is perceived from the results that the parasitic capacitances are higher in the deep inversion region, however; the coupling of parasitic capacitance is weak in GEWE-SiNW due to lower gate metal workfunction at the drain end. Moreover, the influence of drain voltage on Cgs is very less owing to constant depletion charges at the source side which results in almost constant value of Cgs with the change in Vds. With tuning of channel length (Lg) and oxide thickness (tox), the effect of capacitances in GEWE-SiNW further reduces significantly due to quantization effect at such scaled dimensions. Furthermore, Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) have also been calculated with an aim to analyze the device DC and switching performance as they are directly or indirectly linked with parasitic capacitance. Calibrated 3D simulations validate that the GEWE-SiNW MOSFET exhibit 2.57, 34.5 and 2.75 times improvement in TFP, EDP and GBP respectively in comparison to SiNW in the linear region.

This brief presents a comparative performance study of two recently presented techniques, the multiple-input bulk-driven (MI-BD) and the multiple-input bulk-driven quasi-floating-gate (MI-BD-QFG) MOS transistors (MOST). These techniques offer simplified CMOS structures of specific active elements and ensure near rail-to-rail operation capability under extremely low-voltage supply and reduced power consumption. However, to clarify the pros and cons of each technique, two Differential Difference Current Conveyors (DDCC) using MI-BD and MI-BD-QFG are compared. For the purpose of comparison, theoretical analysis such as small-signal model, open-loop gain, terminal resistances, gain bandwidth product, input referred thermal noise and maximum input range of the DDCCs are included. Furthermore, in order to provide a fair performance comparison both of the DDCCs is supplied with 0.4 V and consume same power 140 nW. The DDCCs were fabricated in a standard n-well 0.18 µm CMOS process from TSMC and hence the results are confirmed theoretically and experimentally.

In this paper, an enhanced CMOS recycling folded cascode (RFC) operational amplifier (Op-Amp) is presented. It is based on the high recycling folded cascode (HRFC) in amplifying the transconductance at the output by shorting two nodes in the RFC structure. Compared to the conventional RFC, our circuit is capable to enhance DC gain and unity gain bandwidth (UGBW) in the same power consumption. Moreover, the improvements of the proposed circuit are in better input-referred noise, fast-settling time, input-offset voltage, total harmonic distortion (THD), common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR). Simulation results in 180 nm CMOS standard technology confirm the theoretical results and indicate that our circuit has a good figure of merit (FoM). Compared to the RFC, the proposed HRFC has 1.8 times the UGBW (247 versus 137 MHz) and also has 6 times gain boosting (73 versus 57 dB) in the same power supply (1.8 V), power consumption and driving capacitor load of 5 pF.

Silicon-germanium (Si-Ge) avalanche photodiodes (APDs) have superior gain bandwidth product due to the low impact ionization ratio of silicon. To enable efficient optical transceiver systems, cosimulation environments are essential for optimization of optical devices and transceiver circuitry. A compact Si-Ge APD circuit model, which captures both electrical and optical dynamics over a wide range of multiplication gain, is presented. This model includes effects of carrier transit time, avalanche buildup time and electrical parasitics. Model parameters are extracted by small-signal measurement and impulse response measurement where three gain regimes are discussed corresponding to the different mechanisms of carrier transit time and electrical parasitics. Simulated and measured bandwidth versus gain have a good agreement for APD multiplication gains from M = 1 to M = 17. Excellent matching between simulated and measured 25 Gb/s eye diagrams at M = 2 and M = 5.9 is achieved.

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk-driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC.

In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency ( f T ), gain bandwidth product, transconductance generation factor and so on. The higher I ON / I OFF ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher g m / I D ratio ensures lower bias power of an amplifier.

This paper presents a new technique to improve CMOS recycling folded cascode (RFC) operational amplifier (Op-Amp). Our modification is based on shorting two nodes in the conventional RFC circuit. It causes that the seen resistance from the created new node be half of the conventional RFC counterpart and makes it to double the slew rate. Compared to it, our circuit is also capable to enhance DC gain and unity gain bandwidth (UGBW) with increasing output resistance of differential pair. Moreover, our proposed improvements are in better fast-settling time, input referred noise, input offset voltage, total harmonic distortion (THD), common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) in the same power consumption. Simulation results in 180 nm CMOS process indicates that the proposed amplifier has 1.5 times the unity gain bandwidth (185 MHz versus 125 MHz) and also has 7 times gain boosting (75 dB versus 58 dB) with better figure of merit (FOM) in the same power consumption, driving capacitor load of 10 pF @1.2 V power supply. The results also demonstrate that the temperature sensitivity, power supply variations and process corners have a negligible effect on the proposed amplifier stability.

This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

A voltage-controlled current amplifier/attenuator in a standard 0.35- ${\mu }\text{m}$ CMOS technology is presented. It is based on the resistive mirror method, using non-saturated MOSFETs. An open-loop design with no compensation capacitors provides a high stability and a small occupied chip area of 0.0126 mm2. A current gain dynamic range of 513 (54.2 dB), a gain-bandwidth product of 1.78 GHz at the largest current gain of 35.9 dB, and a maximum power consumption of 250 ${\mu }\text{W}$ with a single supply voltage of 1.3 V are achieved. In addition, an AC current source has been designed, integrated on the same chip, and used as the input of the proposed voltage-controlled amplifier/attenuator.

The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp’s requirements including dc gain, unity gain bandwidth, thermal and 1/ ${f}$ noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 $\mu \text{W}$ from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 $\mu \text{W}$ from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.

We have studied the impact of temperature variation on Dual Metal Gate GaSb-Si NWTFET device performance. Variations in DC parameters namely the transfer characteristics, Threshold Voltage, I on /I off Ratio, Subthreshold Swing has been investigated for temperatures from 250K to 400K. Furthermore, variations in RF performance metrics namely trans-conductance g m , Drain Conductance g d , Parasitics Capacitance C gd C gs , Intrinsic Gain g m /g d , Transconductance Frequency Product TFP, Cutoff Frequency f T , Gain Frequency Product GFP, Gain Bandwidth Product GBP, Transit Time τ for different temperatures have also been studied. Lastly, the variations in Linearity performance metrics namely VIP 2 , VIP 3 , IMD 3 and IIP 3 for different temperatures is studied.

In this paper, transistor sizing of the inverter-based operational transconductance amplifier (OTA), which has been widely used in circuit applications recently, has been implemented with the gm-ID technique. Especially, considering the unit gain bandwidth, this design parameter is optmized with this technique. The proposed inverter-based OTA gain is 25dB, and the unity gain bandwidth value is 4.82 MHz, which is the simulation result, and 4.77 MHz, which is the calculated value. The simulated unit gain bandwidth frequency value, in particular, agrees with the measured value.

The fifth generation (5G) wireless technology will provide the nation’s future telecommunications network, featuring higher bandwidth and data rates with lower delay and power consumption. This shift facilitates the ultra-level of integration, for systems loaded with embedded sensors that are enabled by this technology. A few challenges remain regarding the standards to proper interfacing, security for cellular based services, and ability of portable devices to be employed in this technology. These challenges include high-speed amplifiers and signal processors. Millimeter wave communications with frequencies above 10 GHz for mobile networks may be required to meet the propagation quality demands of this technology. This paper proposes the Graphene Nano Ribbon Field Effect Transistor (GNRFET) device as a potential candidate that fits well in this technology, featuring high frequency amplifiers and high switching speed in digital circuits with ultra-low power consumption. These advantages may be attributed to the high mobility and mean free path of the device, leading to major ballistic carrier transport. The simulation was conducted at a switching speed in the order of 10GHz and 0.7V supply. The device was also employed for high frequency amplifiers, achieving as much as 5.1 THz gain bandwidth product (70GHz at a gain of 75), with very clean output signals. Near 115 dBs attenuation losses for harmonics was determined within the operating bandwidth. This paper details the device model, circuit design, and power consumption, suitable for the 5-G communication system. The nanoscale size of the device provides the ultra-level of integration, incorporating the embedded and IoT devices supporting this technology.

In this paper, the performance of FinFET has been examined by changing the fin width which affects the device performance. The fin width has been changed by keeping the device width fixed and varying the width of the oxide layer by electrical characterization and simulation. The device width is fixed at 50nm and the oxide layer width is varied from 10nm to 3nm. Here five different parameters such as drain current (ID), transconductance (g m ), cutoff frequency (f T ), gain bandwidth product (GBW), and power (P) are computed to study the effect of oxide layer width of the device. It has been observed from the simulation that at lower oxide layer width ID and g m show maximum value, and at medium value of oxide layer width f T and GBW give better performance. The power consumption of FinFET is lesser when the oxide layer width reduces.

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

In this work, we demonstrate In0.52Al0.48As top/backside-illuminated avalanche photodiodes (APD) with dual multiplication layers for high-speed and wide dynamic range performances. Our fabricated top-illuminated APDs, with a partially depleted p-type In0.53Ga0.47As absorber layer and thin In0.52Al0.48As dual multiplication (M-) layer (60 and 88 nm), exhibit a wide optical-to-electrical bandwidth (16 GHz) with high responsivity (2.5 A/W) under strong light illumination (around 1 mW). The measured bias dependent 3-dB O-E bandwidth was pinned at 16 GHz without any serious degradation near the saturation current output. To further increase the speed, we downscaled the active diameter and adopted a back-side illuminated structure with flip-chip bonding for batter optical alignment tolerance. A significant improvement in maximum bandwidth was demonstrated (25 versus 18 GHz). On the other hand, we adopted a thick dual M-layer (200 and 300 nm) and 2 μm absorber layer in the APD design to circumvent the problem of serious bandwidth degradation under high gain (&gt, 100) and high-power operation which significantly enhanced the dynamic range. Due to dual M-layer, the carriers could be energized in the first M-layer then propagate to the second M-layer to trigger the avalanche process. In both cases, despite variation in thickness of the absorber and M-layer, the cascade avalanche process leads to values close to the ultra-high gain bandwidth product (GBP) of around 460 GHz with a responsivity of 0.4 and 1 A/W at unit gain for the thin and thick M-layer devices, respectively. We successfully achieved a good sensitivity of around −20.6 dBm optical modulation amplitude (OMA) at a data rate of 25.78 Gb/s, by packaging the fabricated APDs (thin dual M-layer (60 and 88 nm) version) with a 25 Gb/s trans-impedance amplifier in a 100 Gb/s ROSA package. The results show that, the incorporation of a dual multiplication (M) layer structure in the APD opens a new window to obtaining the higher GBP in order to meet the requirements for high-speed transmission without the need of further downscaling the multiplication layer.

This paper presents the design and optimization of conventional Operational Transconductance Amplifier (OTA) topologies, which can be used in implementation of Electroencephalogram (EEG) pre-amplifier. Gm/ID based systematic approach was used to enhance the performance of Current-Mirror, Telescopic, Folded cascode and Recycled Folded cascode OTA topologies using CMOS transistors working in sub-threshold region. A detailed description of the structure of OTAs, design parameters and trade-offs is presented with a focus to design low-noise and low-power amplifier. The OTAs were designed in a 0.18µm CMOS technology using industry standard Cadence EDA Tool with 1P3M layout. Simulation results show open loop gain of 45.83 dB, 62.63dB, 57.86 dB and 50.13 dB; unity gain bandwidth of 3 kHz, 2 kHz, 3 kHz and 5.5 kHz; NEF of 1.629, 2.7, 0.6 and 7.4 for current-Mirror, telescopic, folded cascode and recycled folded cascode OTAs respectively.

This chapter presents an ultra-low-power folded cascode bulk-driven voltage to current converter, also called an operational transconductance amplifier (OTA), operating in weak inversion or subthreshold region. This folded cascode bulk-driven OTA provides nearly rail-to-rail input common mode range, enough 3-dB bandwidth and gain bandwidth product to process low-amplitude and low-frequency biosignals with sub-100 nW power dissipation. This designed OTA has been employed for multifunction single-input multiple-output and multiple-input single-output type biquadratic filters, notch filters, oscillators, integrators, adders, instrumentation amplifiers, and wave-shaping circuits. This FC-BD-OTA has been converted to a dual-output second-generation current conveyor (CCII+) cell useable for the design of various LV-LP and low-frequency voltage as well as current mode circuits. This designed CCII+ cell has been employed to design biquadratic filters, current mode instrumentation amplifier, analog signal adder, biphase, and three-phase oscillators as well as in some wave-shaping circuits. These applications are designed to process low-frequency (100 mH–500 Hz) biomedical signals. Appendix 1 briefly introduces another symmetric current mirror self-cascode load bulk-driven OTA having three output nodes, which has been utilized to design full wave rectifiers. All these circuits and subcircuits have been designed and simulated in standard n-tub-bulk 180 nm complementary metal oxide semiconductor process technology using Tanner EDA simulator tool of version 16.1.

Microelectromechanical System (MEMS) Sensor technology has revolutionized the electronics industry with its wide array of applications from wearable electronics to precision instrument for biomedical applications. However, two of the most inherent problems with these sensors are low capacitance-to-voltage conversion of sensors and its high susceptibility to noise. Since MEMS sensors have been developed over the years, and as to meet the surging market demands of interface circuits, the need for upgrading its features has led to the integration of more complex designs This paper presents an integrated approach for MEMS switched capacitor-based interface which is implemented using a Low Noise Operational Transconductance Amplifier (OTA) design and a digital clock control block implemented in 65nm CMOS Process. The OTA design composes of a noise buffer preamplifier cascaded to a conventional folded cascode amplifier topology. The OTA design obtained parameters values with an open loop gain of 65.5 dB, Unity gain bandwidth of 8.48 MHz, PSRR+ of 65.2 dB and PSRR-of 93.3 dB and a CMRR of 115 dB. Input referred Noise is at 18.369 nV/√Hz. MEMS sensors signal are initialized at the input as MEMS sensors are beyond the scope of this study. With a MEMS noise model, the obtained noise cancellation ability of the proposed amplification and noise cancellation network is known to be 88.765%. The overall circuit covers a chip area of $242\ \mathbf{um}\times 705\ \mathbf{um}$

In this paper we unveil of a new structure in which a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is paralleled with a Tunneling Field Effect Transistor (TFET) to increase on-state current. In order to enhance tunneling current injection rate in the device, workfunction engineering in gate and substrate electrodes and doping engineering in channel (source pocket) are utilized. For further on-state current enhancement of device, thermionic injection mechanism is used by incorporating a MOSFET in the structure. In addition, hetero gate dielectric is used to reduce parasitic capacitances. Our analysis show PTM-FET transistor has several excellences in comparison to DW HGD SP TFET in terms of transconductance, Ion/Ioff current ratio, short channel effects like DIBL, Early voltage, maximum transducer power gain, unilateral power gain, gain bandwidth product, unity gain frequency and parasitic capacitances. The mentioned advantages for PTM-FET transistor can be a window of utilizing this device in both low power and high performance integrated circuit applications.

In this paper, the direct bonding InGaAs/Si avalanche photodiode (APD) with certain gain is developed. This structure separates the optical absorption region (InGaAs) from the multiplication region (Si). Avalanche multiplication takes place in the Si layer after the carriers injected from the absorption region. InGaAs and Si wafer are connected together by wafer bonding technology. The interface quality of InGaAs / Si material is good through optimizing the physical and chemical cleaning methods and bonding conditions of InGaAs/InP and Si epitaxial wafers. The InGaAs / Si APD is fabricated by conventional semiconductor process. The gain of InGaAs / Si APD is 43 at 38V. Further optimization of the process can obtain lower dark current and higher gain bandwidth product. This kind of device can be used for long-distance optical fiber communication.

This paper has proposed a new architecture for variable gain amplifier (VGA) built in the 0.1S$\mu$m CMOS technology. In this paper, a new definitive approach is proposed for achieving a large band range of DC gain, acceptable bandwidth (-3dB) with low power consumption and high linearity. This proposed VGA was designed on the Cadence Virtuoso tool for receiver system used in RF, consisting of trans-impedance amplifier and trans-conductor amplifier which are in linear mode. This VGA also attains DC gain range from -35 to 19 dB, and bandwidth is around 25.8 MHz (-3dB). Meanwhile, the proposed VGA, Unity Gain Bandwidth of is nearly 3.32GHz with noise Figure nearly 20dB. Overall circuit consumes total power approximately 2.3mW.

This paper presents a fully digital synthesizable Operational Amplifier (OPAMP) based on digital standard cells. The OPAMP's gain is enhanced by the combination of the all-inverter-based negative resistance loads and the four-stage cascade structure with Nested Feed Forward Compensation (NFFC). Moreover, this paper uses NAND-NOR pairs to improve the common mode input range. Since the proposed OPAMP only consists of digital standard cells, it is described in Verilog code, and its layout is implemented using automatic placement and route (APR) tool. The proposed circuit is implemented in 28nm CMOS and the post-layout simulation results show that the proposed circuit achieves a DC gain of 35dB and a unity gain bandwidth (UGB) of 1.73GHz under 0.9V power supply.

This paper presents the description and analysis of the design and HSPICEbased simulation results of very low-voltages (LVs) power supplies and highperformance specifications CMOS gate-driven (GD) operational amplifier (OpAmp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from -0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 ⁄√ at 1MHz, the positive slew rate is 11.37 ⁄ , the negative slew rate is 11.39 ⁄ , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits

To design data converters main challenges are high resolution, high speed, and low power. Operational amplifiers (op-amps) are core building blocks in such mixed signal systems to overcome these issues. As high resolution is linked to op-amp's high dc gain and high speed demands single pole response and large unity gain frequency. This paper deals with design of two stage opamp with class AB as output stage and it has been simulated in 0.18um TSMC CMOS technology. This design achieves high low frequency gain(92dB), good gain bandwidth product(19.07MHz) and low power. To stabilize this op-amp techniques used are Miller compensation, which has compensation capacitor ( $C_{m}$ ) and zero nulling resistor ( $R_{Z}$ ), in this design $R_{Z}$ has been implemented with PMOS transistor along with transconductance ( $g_{m2}$ ) of second stage, which is set by current is this stage in order to push non dominant pole ( $f_{nd}$ ) to a higher frequency in order to get better gain band width product(GBW) and good phase margin.

This paper presents a new constant transconductance (gm) technique for rail-to-rail CMOS operational amplifier input stages. The proposed technique can provide a constant transconductance value over the whole common-mode range with low current consumption. Also, the technique ensures no additional current at the output of the rail-to-rail input stage. To prove its advantages, the technique was integrated in a chopper stabilized operational amplifier. The simulation results show a transconductance variation of only 4% and a constant unity gain bandwidth.

Differential amplifier is an analog component. which is used as an amplifier whenever a circuit contains more than one input. A differential amplifier is a basic primitive component in an operational amplifier. Differential amplifier contains three legs. In which two legs for the input signal to be amplified, the third leg used as output. The differential amplifier can be configured by bipolar technology or with Metal oxide semiconductor technology also. When the input non-inverted leg which acts as a comparator is applied as input, if any signal applied to invert leg of the differential amplifier it will be used as an amplifier. In this proposed article, the operational amplifier with high gain of 72dB is implemented, the Slew rate of 122 V/µs, Gain bandwidth product of 4.60 MHz Dual-stage operational amplifier will enhance the amplification in a better way when the single-stage amplifier is compared In this article, a dual-stage operational amplifier using CMOS 45nm Technology is implemented.

This paper presents a fast-response output-capacitorless low-dropout regulator (OCL-LDO) using a high slew-rate input stage and improved multipath nested Miller compensation (MNMC). With the specially-designed input stage, the quality factor (Q) of the transfer loop is greatly reduced. The circuit is implemented in a standard 65-nm CMOS process. The total on-chip compensation capacitance is 0.5 pF only. The designed OCL-LDO regulator features over 150 MHz unity-gain bandwidth (UGB) at zero load and keeps UGB higher than 100 MHz up to 45 mA loading. For the maximum 60-mA load transient with 10-ns edge time, the voltage spikes are controlled around 20 mV.

This paper presents a novel high speed operational amplifier using a-IGZO TFTs for a given technology, without changing device structure, processing conditions and materials. In the proposed design, a negative capacitance generator (NCG) is employed, using a-IGZO TFTs, which is connected to the output of a positive feedback operational amplifier. This technique helps to move the output pole of the amplifier to very high frequency by reducing the overall equivalent capacitance (C eq ) at the output node, as the negative capacitance is in parallel with C eq . By using this technique, the unity gain bandwidth (GB) of the opamp is increased from 486 kHz to 1.474 MHz without compromising other performance metrics, such as, gain and stability (phase margin). However power consumption is increased from 0.3mW to 0.6 mW, when the simulations took place with in-house IGZO TFT models. Both NCG and the amplifier were designed with a minimum feature size of 10 μm and a power supply of 10V and 15V, respectively.

In recent years, switched-capacitor (SC) structure has been widely used in many electronic fields, such as analog to digital converter (ADC) and digital to analog converter (DAC). The vital part in the SC structure is operational amplifier (Op-Amp), to improve the performance of SC structure, a good operational amplifier is necessary. In this paper, based on 0.18µm process, we proposed two types of differential Op-Amps: traditional differential structure and fully differential telescopic structure. Aiming to realize better frequency performance, we compared this two types and find out the telescopic structure has much better unity gain bandwidth (UGBW) up to 690MHz with similar small signal gain and phase margin.

The article presents the results of the development and measurements of a specialized integrated circuit of an instrumentation amplifier (IA) with indirect negative current feedback. The schematic and the measurement results of the main characteristics for a silicon-on-insulator metal-oxide-semiconductor instrumentation amplifier are presented. The amplifier is intended for use as a part of a sensor network for monitoring the state of high-temperature objects. The temperature range of the instrumentation amplifier is up to 200 °C. Instrumentation amplifier has 11.8 MHz gain bandwidth product with a 3.3 V supply voltage. The measured gain is 27.50 dB and the error in setting the gain was 0.27 dB, the 3 dB bandwidth is 500 kHz.

In various signal processing applications, the performance of the data acquisition circuits is depended upon the performance of the amplifier. On the other hand, the noise signal may saturate the system. The operational amplifier is found to be the most efficient amplifier for signal processing circuits. In literature, several operational amplifiers were designed using Bipolar junction transistors, Field effect transistors and CMOS devices. But the power consumption has limitations on design with BJT and CMOS devices. To overcome this, new alternative devices are required. The minimum parasitic interconnection elements and low supply voltage will enhance the performance. To enhance these requirements, this paper presents a FinFET-based OP-AMP and OTA design with low power, very high unity gain bandwidth (UGB) and high open-loop gain (DC gain). The FinFET-based circuit is designed using 32 nm technology. The proposed circuit has higher driving capacity and is highly stable.

In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

In this paper an improved version of the design procedure of two-stage CMOS operational amplifier employing a Miller capacitor and a current buffer is presented. Unlike the op amp obtained from the previously reported design procedure, in which the unity gain frequency is approximated by the gain bandwidth product, the resulting op amp from the proposed procedure has frequency response characteristics much closer to the desired values. Design example of the proposed procedure is given and the results compared to the previous method.

This paper proposes a novel operational amplifier (OPA) voltage-controlled oscillator (VCO) circuits on the basis of impedance converters. The VCO can operate over a frequency range exceeding unity-gain bandwidth due to the location of the tank circuit, not at the output of the OPA, but at the noninverting input. The paper presents the mathematical modeling of oscillated amplitude and start-up conditions. The simulation results confirm the theoretical achievements. The designed and simulated VCO uses an ultra-low noise wideband OPA LMH6629MF, covers a frequency band between 0.830 GHz and 1.429 GHz, and exhibits a maximum in-band total harmonic distortion (THD) of 1.7%. It has a maximum in-band phase noise of &minus, 139.3 dBc/Hz at 100 kHz offset frequency and has an outstanding value of a standard figure of merit (FoM) of &minus, 198.6 dBc/Hz. The zero-peak amplitude of output voltage is from 3.2 V to 4 V for all generated frequencies at a supply voltage of &plusmn, 5 V. The fabricated prototype-oscillator based on OPA LMH6624 operates at a frequency of 583.1 MHz with a power level of 0 dBm.

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/&mu, m to 0.1 fF/&mu, m. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

This work represents a novel low noise amplifier, designed for biomedical front-end applications. The proposed circuit is designed using 180 nm CMOS technology. The simulation results exhibit very good performance showing a gain of 57.9 dB and unity gain bandwidth of 330 KHz. The proposed design shows enhanced phase margin of 84 degree due to its sub-threshold region of operation for the devices. The circuit performs under the supply voltage of 1.8 V and consumes only 400 nW of DC Power. The input-referred noise voltage of the designed circuit is obtained as$0.6\mu V/\sqrt {HZ} $ at 5 KHz, which makes it suitable for biomedical applications. Also, the CMRR of the designed circuit is obtained as 82.6 dB.

International audience; Owing to its low-cost, high-yield, and dense integration ability, silicon nanophotonics is a good candidate to tackle the needs of exponentially growing communications in data centers, high-performance computers, and cloud services. Moreover, a number of nanophotonic functions are now available on a single chip, as they take advantages of silicon-foundry process maturity and epitaxial germanium integration. Optical photodetectors are key building blocks in the library of group-IV components and their performances are quite successful nowadays. In particular, silicon-germanium waveguide-integrated photodetectors are fixing new standards for next generation of on-chip interconnects in terms of compactness, speed, power consumption and cost. Indeed, conventional pin photodetectors yield good responsivities (~1 A/W in a 1.5 µm wavelength range), high bandwidths (~50 GHz), and dark currents well below 1 µA. Despite recent advances, their optical power sensitivities remain rather modest and speeds are limited to 25 Gbps only, however. Compensating for the insufficient photodetector sensitivity requires higher transmitter output powers and therefore higher energy consumption. Additional energy savings can be obtained by eliminating receiver electronics. Alternatively, an appealing approach is to exploit device structures with an internal multiplication gain to lower even more the power budget and improve energy efficiency of chip-based optical links. In this work, we report on waveguide-integrated photodetectors with lateral silicon-germanium-silicon heterojunctions. Here, we present avalanche photodetectors fabricated on 200-mm silicon-on-insulator wafers using complementary metal-oxide-semiconductor-compatible processes. Devices operate in the low-gain-regime to facilitate high-speed link operations at 1.55 µm wavelengths. An error-free signal detection was achieved at 28 Gbps, with power sensitivity of-11 dBm for 10-9 bit-error-rate, which is a relevant link rate for emerging chip-scale optical interconnects.

Low Power Dissipation is an emerging challenge in the current electronics industry. Area shrinking has found the most prominent place and is the foundation of every constricted size in the utilization of CMOS circuits in Integrated Circuit Manufacturing. Functionality in terms of rapidity, dissipation of power, etc. are strongly influenced by the dimensions of transistors in many CMOS Integrated Circuits. The significant formulation parameters in CMOS circuit design to perform optimization of the above-mentioned parameters, and various techniques were projected earlier to a maximum extent possible. Latency, Power, and Dimension are significant parameters in the design of CMOS based IC design. Most analog circuit reduction in terms of size as parameter typically describes solitary or many objectives-controlled optimization issues. The eminent challenges with regards to size and power dissipation can be described as problems that are typically encountered under certain conditions. In this study, the design of a two-stage CMOS Differential Amplifier applying the nature-inspired Grey Wolf Algorithm for optimizing the area and power is utilized. To enhance the formulation terms concerning important considerations such as the amount incurred, strength, and functionality; a computerized formulation approach is used. This formulated design proposal will meet specifications such as positive and negative Slew Rate, Unity Gain Bandwidth and Phase Margin, etc. Chaos theory can be induced into the Grey Wolf Optimization Algorithm (CGWO) with the help of speeding global convergence metric i.e. Speed. The results obtained from CGWO are then analyzed with the functionality of other prevailing optimization techniques employed in the analog circuit sizing. Depending on the investigations, CGWO functions reduce the dimensions of the circuit and analyze the prevailing techniques by achieving a healthier rate of convergence and power dissipation with low value.

In this paper, a folded cascode operational amplifier is designed and analysed by using 0.13 µm CMOS technology. Several analyses such as DC analysis and AC analysis are carried out to analyse the performances of the proposed folded cascode op-amp. Through the simulation of Mentor Graphics, under 3.3 V power supply, the circuit’ s DC gain is 32.3590 dB, the phase margin is 83.754 degree with high stability, the bandwidth is larger than 10 MHz, the unity gain bandwidth is as high as 906.8953 MHz and the power dissipation is 86.9774 mW.